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Note for Analog And Digital Electronics - ADE By vtu rangers

  • Analog And Digital Electronics - ADE
  • Note
  • Visvesvaraya Technological University Regional Center - VTU
  • 6 Topics
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Guide for Analog and Digital Electronics Module 1 Principle of Operation: Depletion Region D + e VDS + VGS=0 - - ID G VDD VGS=0 N P P e VDD e e S When a positive Drain (D)-Source (S) voltage(VDS) is applied with Gate(G) shorted with the Source (S) terminal (VGS=0), the electrons in the N-Channel are attracted to the Drain (D) terminal and due to the flow of electrons, Drain Current (ID) is established. The value ID depends on the applied VDS and the resistance of the N-Channel. There is uniform voltage drop across the channel and the two P-N junctions are reversed biased. This results in increase of width of the depletion regions. The depletion regions are wider near the drain region. ID increases linearly with the increase of VDS till saturation effect sets in. The value of VDS where the saturation effect sets in is referred to as Pinch-Off (VP) voltage. When VDS reaches VP, the value of ID remain same with the further increase of VDS. The Gate–Source voltage (VGS) is to control the value ID. When a negative voltage is applied between Gate and Source terminals, there is an increase of width of the depletion layers and as a result the value of Drain Current (ID) decreases. As the value VGS is made further negative, at a certain value of negative VGS, the Drain Current become zero. This voltage is referred as GateSource pinch-Off voltage. The relation between the Drain Current, ID for a given value of VGS is given by 2  V  ID  IDSS 1  GS  VP   Where IDSS is the Drain to Source Current when Gate is shorted with the Source. VP is the Pinch –Off voltage. The drain resistance (rd) in the saturation region is given by r0 Where r0 is the resistance at VGS=0 and VP is the Pinch –Off voltage. rd  2  VGS  1   VP   Page: 2

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Guide for Analog and Digital Electronics Module 1 Q2. Explain the Characteristics of N-Channel and P-Channel Junction Field Effect Transistor. Answer: N-Channel Junction Field Effect Transistor (JFET) Output Characteristic ID(mA) 6 5 Ohmic region Breakdown region Saturation region VGS=0V IDSS 4 VGS=-1V 3 2 VGS=-2V 1 VGS=-3V VGS=-4V 5 10 15 VDS(V) 20 25 The output characteristic of the N-Channel JFET is shown in the above diagram. Drain Current (ID) is plotted against Drain-Source voltage (VDS) keeping the Gate-Source voltage (VGS) constant. As shown in the diagram, at lower value of Drain-Source voltage (VDS), the Drain Current (ID) is proportional Drain-Source voltage(VDS) and it follows the Ohm’s law. This region is referred as Ohmic region. As Drain-Source voltage (VDS) increases further, at a certain value Drain Current (ID) does not increase and this region as shown in the diagram is referred as Saturation region. If Drain-Source voltage(VDS) is goes on increase, then after certain value of Drain-Source voltage(VDS), the Drain Current (ID) increases rapidly with small increase of Drain-Source voltage(VDS) as shown in the diagram. This region is referred as breakdown region. Page: 3

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Guide for Analog and Digital Electronics Module 1 Transfer Characteristic ID(mA) ID(mA) 6 6 5 5 VGS=0 IDSS 4 4 VGS= -1V 3 3 2 2 1 1 VGS= -2V VGS= -3V VGS= -4V VGS (V) -4 -3 -2 -1 0 0 5 10 15 20 The transfer characteristic of the N-Channel DE-MOSFET is shown in the above diagram. Drain Current (ID) is plotted against Gate-Source voltage (VGS) keeping the Drain-Source (VDS) voltage constant. Page: 4 VDS(V)

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Guide for Analog and Digital Electronics Module 1 Q3.Explain the construction and principle of operation of N-Channel and P-Channel Depletion Metal Oxide Semiconductor Field Effect Transistor (DE-MOSFET). Answer: N-Channel Depletion Metal Oxide Semiconductor Field Effect Transistor (DE-MOSFET) Construction: Cross Section of an N-Channel DE-MOSFET Source(S) Gate(G) Drain(D) Metal Contract SiO2 N+ N N+ N+ region N-Channel P-Substrate Substrate(SS) The above figure shows the construction of DE-MOSFET. It consists of a P-type substrate. Two N+ type regions linked by an N-channel are formed in the substrate. The source and the drain terminals are formed by connecting metal contacts to the two N+ regions. The gate terminal is connected to the insulating silicon dioxide (SiO2) layer on the top of the N-channel. There is no direct connection between the gate terminal and the channel. Principle of Operation: When a positive voltage is applied between drain and source terminals (+VDS), with gate shorted to the source (VGS=0), then there is a flow of electrons towards drain terminal through N-channel as the electrons are attracted to the positive terminal at drain. This constitute Drain Current (ID). The value of ID increases with increase of VDS up to a certain value of VDS. After that value of VDS, the ID remain constant and this value is referred as IDSS (Drain Current with Drain shorted with the source). For positive gate to source voltage, the electrons (minority carrier) in the P-Substrate are attracted towards the gate terminal and concentration of electrons at the N-channel increases. As a result, the drain current increases. As the application of positive drain to source voltage Page: 5

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