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Note for VLSI Design - VLSI By Amity Kumar

  • VLSI Design - VLSI
  • Note
  • Amity University - AMITY
  • Computer Science Engineering
  • 9 Topics
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The graph in figure2 compares the various technologies available in ICs. Figure 2.Comparison of available technologies From the graph we can conclude that GaAs technology is better but still it is not used because of growing difficulties of GaAs crystal. CMOS looks to be a better option compared to nMOS since it consumes a lesser power. BiCMOS technology is also used in places where high driving capability is required and from the graph it confirms that, BiCMOS consumes more power compared to CMOS. Levels of Integration:i) ii) iii) iv) v) Small Scale Integration:- (10-100) transistors => Example: Logic gates Medium Scale Integration:- (100-1000) => Example: counters Large Scale Integration:- (1000-20000) => Example:8-bit chip Very Large Scale Integration:- (20000-1000000) => Example:16 & 32 bit up Ultra Large Scale Integration:- (1000000-10000000) => Example: Special processors, virtual reality machines, smart sensors 2

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Basic MOS Transistors: Why the name MOS? We should first understand the fact that why the name Metal Oxide Semiconductor transistor, because the structure consists of a layer of Metal (gate), a layer of oxide (Sio2) and a layer of semiconductor. Figure 3 below clearly tell why the name MOS. . Figure 3.cross section of a MOS structure We have two types of FETs. They are Enhancement mode and depletion mode transistor. Also we have PMOS and NMOS transistors. In Enhancement mode transistor channel is going to form after giving a proper positive gate voltage. We have NMOS and PMOS enhancement transistors. In Depletion mode transistor channel will be present by the implant. It can be removed by giving a proper negative gate voltage. We have NMOS and PMOS depletion mode transistors. N-MOS enhancement mode transistor:This transistor is normally off. This can be made ON by giving a positive gate voltage. By giving a +ve gate voltage a channel of electrons is formed between source drain. P-Mos enhancement mode transistors:This is normally on. A Channel of Holes can be performed by giving a –ve gate voltage. In P-Mos current is carried by holes and in N-Mos its by electrons. Since the mobility is of holes less than that of electrons P-Mos is slower. 3

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N-MOS depletion mode transistor:This transistor is normally ON, even with Vgs=0. The channel will be implanted while fabricating, hence it is normally ON. To cause the channel to cease to exist, a – ve voltage must be applied between gate and source. NOTE: Mobility of electrons is 2.5 to 3 times faster than holes. Hence P-MOS devices will have more resistance compared to NMOS. Enhancement mode Transistor action:- 4

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Figure 8(a)(b)(c) Enhancement mode transistor with different Vds values To establish the channel between the source and the drain a minimum voltage (Vt) must be applied between gate and source. This minimum voltage is called as “Threshold Voltage”. The complete working of enhancement mode transistor can be explained with the help of diagram a, b and c. a) Vgs > Vt Vds = 0 Since Vgs > Vt and Vds = 0 the channel is formed but no current flows between drain and source. b) Vgs > Vt Vds < Vgs - Vt This region is called the non-saturation Region or linear region where the drain current increases linearly with Vds. When Vds is increased the drain side becomes more reverse biased(hence more depletion region towards the drain end) and the channel starts to pinch. This is called as the pinch off point. c) Vgs > Vt Vds > Vgs - Vt This region is called Saturation Region where the drain current remains almost constant. As the drain voltage is increased further beyond (Vgs-Vt) the pinch off point starts to move from the drain end to the source end. Even if the Vds is increased more and more, the increased voltage gets dropped in the depletion region leading to a constant current. The typical threshold voltage for an enhancement mode transistor is given by Vt = 0.2 * Vdd. 5

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