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Note for Computer Organisation and Architecture - COA by Anil Reddy Maram

  • Computer Organisation and Architecture - COA
  • Note
  • Sagi Ramakrishnam Raju Engineering College - SRKR
  • Computer Science Engineering
  • B.Tech
  • 4 Topics
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REGISTER TRANSFER AND MICRO OPERATIONS Register Transfer Language ¾ The symbolic notation used to describe the micro-operation transfers amongst registers is called Register transfer language. ¾ The term "register transfer" means the availability of hardware logic circuits that can perform a stated micro-operation and transfer the result of the operation to the same or another register. ¾ The word “Language “is borrowed from programmer’s, who apply this term to programming languages Register Transfer Information transferred from one register to another is designated in symbolic form by means of replacement operator. R2 ! R1 It denotes the transfer of the data from register R1 into R2. Normally we want the transfer to occur only in predetermined control condition. This can be shown by following if-then statement: if (P=1) then (R2 ! R1) Here P is a control signal generated in the control section. Fig:- Block Diagram of register Control Function A control function is a Boolean variable that is equal to 1 or 0. The control function is shown as: P: R2 ! R1 The control condition is terminated with a colon. It shows that transfer operation can be executed only if P=1. Implementation of controlled transfer P: R2 !R1 MATERIAL PREPARED BY ANIL REDDY [2/4 CSE]

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Block diagram Timing Diagram • The same clock controls the circuits that generate the control function and the destination register • • • • Registers are assumed to use positive-edge-triggered flip-flops If two or more operations are to occur simultaneously, they are separated with commas P: R3 ¬ R5, MAR ¬ IR Here, if the control function P = 1, load the contents of R5 into R3, and at the same time (clock), load the contents of register IR into register MAR Basic Symbols for Register Transfers MATERIAL PREPARED BY ANIL REDDY [2/4 CSE]

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Bus and Memory Transfer Bus Transfer The most efficient way to transfer data is by using a common bus system, which is configured using common bus registers in a multiple register. The structure of the bus consists of a set of lines. These lines are registers of one bit each that transfer only one data at a time. The data transfer is controlled by the control signals. Control signals determine which register is to be selected during each register transfer. To construct a common bus system, two methods are used: 1. Using Multiplexer 2. Using Three States Bus Buffers Multiplexer: The multiplexers select the source register whose binary information is then placed on the bus. The selection lines are connected to the selection inputs of the multiplexers and choose the bits of one register. The construction of a bus system for four registers is shown in Fig: - Bus system for four registers Fig: - Bus system for four registers Each register has four bits, numbered 0 through 3. In order not to complicate the diagram with 16 lines crossing each other, we use labels to show the connections from the outputs of the registers to the inputs of the multiplexers. For example, output 1 of register A is connected to input 0 of MATERIAL PREPARED BY ANIL REDDY [2/4 CSE]

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MUX 1 because this input is labelled A1. Thus MUX 0 multiplexes the four 0 bits of the registers and soon. The two selection lines S1 and S0 are connected to the selection inputs of all four multiplexers. The selection lines choose the four bits of one register and transfer them into the four-line common bus. When S1S0 = 00, the 0 data inputs of all four multiplexers are selected and applied to the outputs that form the bus. This causes the bus lines to receive the content of register A since the outputs of this register are connected to the 0 data inputs of the multiplexers. Similarly, register B is selected if S1S0 = 01, and so on. Table shows the register that is selected by the bus for each of the four possible binary value of the selection lines. Function table for bus In general, a bus system will multiples k registers of n bits each to produce an n-line common bus. The number of multiplexers needed to construct the bus is equal to n, the number of bits in each register. The size of each multiplexer must be k ×1 since it multiplexes k data lines. The transfer of information from a bus into one of many destination registers can be accomplished by connecting the bus lines to the inputs of all destination registers and activating the load control of the particular destination register. When the bus is includes in the statement, the register transfer is symbolized as follows: BUS ! C, R1 ! BUS The content of register C is placed on the bus, and the content of the bus is loaded into register R1 by activating its load control input. R1 ! C Three-state bus buffers A bus system can constructed with three-state gates instead of multiplexers. A three-state gate is a digital circuit that exhibits three states. State 1: Signal equivalent to Logic 1 Also, State 2: Signal equivalent to Logic 0 State 3: High Impedance State (behaves as open circuit) The high-impedance state behaves like an open circuit, which means that the output disconnected and does not have logic significance. Moreover, The most commonly used design of a bus system is the buffer gate. MATERIAL PREPARED BY ANIL REDDY [2/4 CSE]

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