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Note for Advanced Microprocessor - AM by sujan basak

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DATASHEET 80C286 FN2947 Rev.3.00 January 28, 2008 High Performance Microprocessor with Memory Management and Protection Features Description • Compatible with NMOS 80286 • Wide Range of Clock Rates - DC to 25MHz (80C286-25) - DC to 20MHz (80C286-20) - DC to 16MHz (80C286-16) - DC to 12.5MHz (80C286-12) - DC to 10MHz (80C286-10) • Static CMOS Design for Low Power Operation - ICCSB = 5mA Maximum - ICCOP = 185mA Maximum (80C286-10) 220mA Maximum (80C286-12) 260mA Maximum (80C286-16) 310mA Maximum (80C286-20) 410mA Maximum (80C286-25) • High Performance Processor (Up to 19 Times the 8086 Throughput) • Large Address Space • 16 Megabytes Physical/1 Gigabyte Virtual per Task • Integrated Memory Management, Four-Level Memory Protection and Support for Virtual Memory and Operating Systems • Two 80C86 Upward Compatible Operating Modes - 80C286 Real Address Mode - PVAM • Compatible with 80287 Numeric Data Co-Processor • High Bandwidth Bus Interface (25 Megabyte/Sec) • Available In - 68 Pin PGA (Commercial, Industrial, and Military) - 68 Pin PLCC (Commercial and Industrial) The Intersil 80C286 is a static CMOS version of the NMOS 80286 microprocessor. The 80C286 is an advanced, highperformance microprocessor with specially optimized capabilities for multiple user and multi-tasking systems. The 80C286 has built-in memory protection that supports operating system and task isolation as well as program and data privacy within tasks. A 25MHz 80C286 provides up to nineteen times the throughput of a standard 5MHz 8086. The 80C286 includes memory management capabilities that map 230 (one gigabyte) of virtual address space per task into 224 bytes (16 megabytes) of physical memory. The 80C286 is upwardly compatible with 80C86 and 80C88 software (the 80C286 instruction set is a superset of the 80C86/80C88 instruction set). Using the 80C286 real address mode, the 80C286 is object code compatible with existing 80C86 and 80C88 software. In protected virtual address mode, the 80C286 is source code compatible with 80C86 and 80C88 software but may require upgrading to use virtual address as supported by the 80C286’s integrated memory management and protection mechanism. Both modes operate at full 80C286 performance and execute a superset of the 80C86 and 80C88 instructions. The 80C286 provides special operations to support the efficient implementation and execution of operating systems. For example, one instruction can end execution of one task, save its state, switch to a new task, load its state, and start execution of the new task. The 80C286 also supports virtual memory systems by providing a segment-not-present exception and restartable instructions. Ordering Information PACKAGE PGA PLCC TEMP. RANGE 10MHz 0oC to +70oC - 12.5MHz CG80C286-12 16MHz CG80C286-16 -40oC to +85oC IG80C286-10 IG80C286-12 - -55oC to +125oC 59629067801MXC 59629067802MXC - 0oC to +70oC -40oC to +85oC FN2947 Rev.3.00 January 28, 2008 IS80C286-10 20MHz CG80C286-20 25MHz PKG. NO. - G68.B - - G68.B - - G68.B CS80C286-12 CS80C286-16 CS80C286-20 IS80C286-12 IS80C286-16 IS80C286-20 CS80C286-25 - N68.95 N68.95 Page 1 of 65

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80C286 Pinouts D12 D13 D14 D4 D5 D6 D7 ERROR 43 45 47 49 51 38 40 42 44 46 48 50 53 52 ERROR NC A2 A1 32 33 55 54 NC BUSY VCC CLK 30 31 57 56 INTR NC A3 RESET 28 29 59 58 NMI NC A5 A4 26 27 61 60 PEREQ VSS A7 A6 24 25 63 62 READY VCC A9 A8 22 23 65 64 HLDA HOLD A11 A10 20 21 67 66 M/IO COD/INTA A13 A12 18 19 16 14 12 10 8 6 4 2 68 NC LOCK 17 15 13 11 9 7 5 3 1 A12 A15 A17 A19 A21 A22 PEACK S1 NC A16 A18 A20 VSS A23 S0 D15 D11 D3 41 36 PIN 1 INDICATOR BHE NC D10 D2 39 34 D9 D1 37 D0 D8 D0 35 A0 A14 VSS 68 LEAD PGA Component Pad View - As viewed from underside of the component when mounted on the board. D14 D13 D12 D11 D10 D9 D8 VSS D7 D6 D5 D4 D3 D2 D1 D0 51 49 47 45 43 41 39 37 35 50 48 46 44 42 40 38 36 34 D0 A0 33 32 A1 A2 VCC ERROR 52 53 BUSY NC 54 55 NC INTR 56 57 31 30 CLK NC NMI 58 59 29 28 RESET A3 VSS PEREQ 60 61 27 26 A4 A5 VCC READY 62 63 25 24 A6 A7 14 16 19 18 A12 A13 1 3 5 7 9 11 13 15 17 A12 12 A14 10 A15 8 A16 6 A17 4 A18 2 A19 68 A20 NC A21 LOCK VSS A11 A22 A9 A10 A23 A8 20 PEACK 22 21 S0 23 67 S1 65 66 NC 64 M/IO NC HLDA BHE HOLD COD/INTA PIN 1 INDICATOR FN2947 Rev.3.00 January 28, 2008 D15 NC ERROR 68 LEAD PGA P.C. Board View - As viewed from the component side of the P.C. board. Page 2 of 65

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80C286 Pinouts (Continued) LOCK M/IO COD/INTA HLDA HOLD READY VCC PEREQ VSS NMI NC INTR NC NC BUSY ERROR NC 68 LEAD PLCC P.C. Board View - As viewed from the component side of the P.C. board. PIN 1 INDICATOR MOLD MARK DOES NOT INDICATE PIN 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 BHE NC NC S1 S0 PEACK A23 A22 VSS A21 A20 A19 A18 A17 A16 A15 A14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 D15 D7 D14 D6 D13 D5 D12 D4 D11 D3 D10 D2 D9 D1 D8 D0 VSS A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 RESET VCC CLK A2 A1 A0 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Functional Diagram ADDRESS UNIT (AU) ADDRESS LATCHES AND DRIVERS SEGMENT BASES OFFSET ADDER SEGMENT LIMIT SEGMENT CHECKER SIZES PHYSICAL ADDRESS ADDER PREFETCHER BUS CONTROL DATA TRANSCEIVERS 6-BYTE PREFETCH QUEUE ALU REGISTERS CONTROL PROCESSOR EXTENSION INTERFACE A23 - A0, BHE, M/IO PEACK PEREQ READY, HOLD, S1, S0, COD/INTA, LOCK, HLDA D15 - D0 BUS UNIT (BU) RESET 3 DECODED INSTRUCTION INSTRUCTION DECODER QUEUE INSTRUCTION UNIT (IU) CLK VSS VCC EXECUTION UNIT (EU) NMI BUSY INTR ERROR FN2947 Rev.3.00 January 28, 2008 Page 3 of 65

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80C286 Pin Descriptions The following pin function descriptions are for the 80C286 microprocessor. SYMBOL PIN NUMBER TYPE DESCRIPTION CLK 31 I SYSTEM CLOCK: provides the fundamental timing for the 80C286 system. It is divided by two inside the 80C286 to generate the processor clock. The internal divide-by-two circuitry can be synchronized to an external clock generator by a LOW to HIGH transition on the RESET input. D15 - D0 36 - 51 I/O DATA BUS: inputs data during memory, I/O, and interrupt acknowledge read cycles; outputs data during memory and I/O write cycles. The data bus is active HIGH and is held at high impedance to the last valid logic level during bus hold acknowledge. A23 - A0 7-8 10 - 28 32 - 43 O ADDRESS BUS: outputs physical memory and I/O port addresses. A23 - A16 are LOW during I/O transfers. A0 is LOW when data is to be transferred on pins D7 - D0 (see table below). The address bus is active High and floats to three-state off during bus hold acknowledge. BHE 1 O BUS HIGH ENABLE: indicates transfer of data on the upper byte of the data bus, D15 - D8. Eight-bit oriented devices assigned to the upper byte of the data bus would normally use BHE to condition chip select functions. BHE is active LOW and floats to three-state OFF during bus hold acknowledge. BHE AND A0 ENCODINGS S1, S0 4, 5 O BHE VALUE A0 VALUE 0 0 Word transfer 0 1 Byte transfer on upper half of data bus (D15 - D8) 1 0 Byte transfer on lower half of data bus (D7 - D0) 1 1 Reserved FUNCTION BUS CYCLE STATUS: indicates initiation of a bus cycle and along with M/IO and COD/lNTA, defines the type of bus cycle. The bus is in a TS state whenever one or both are LOW. S1 and S0 are active LOW and are held at a high impedance logic one during bus hold acknowledge. 80C286 BUS CYCLE STATUS DEFINITION FN2947 Rev.3.00 January 28, 2008 COD/INTA M/IO S1 S0 0(LOW) 0 0 0 Interrupt acknowledge 0 0 0 1 Reserved 0 0 1 0 Reserved 0 0 1 1 None; not a status cycle 0 1 0 0 If A1 = 1 then halt; else shutdown 0 1 0 1 Memory data read 0 1 1 0 Memory data write 0 1 1 1 None; not a status cycle 1(HIGH) 0 0 0 Reserved 1 0 0 1 I/O read 1 0 1 0 I/O write 1 0 1 1 None; not a status cycle 1 1 0 0 Reserved 1 1 0 1 Memory instruction read 1 1 1 0 Reserved 1 1 1 1 None; not a status cycle BUS CYCLE INITIATED Page 4 of 65

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