Some Fundamental Concepts
Fundamental Concepts Processor fetches one instruction at a time and perform the operation specified. Instructions are fetched from successive memory locations until a branch or a jump instruction is encountered. Processor keeps track of the address of the memory location containing the next instruction to be fetched using Program Counter (PC). Instruction Register (IR)
Executing an Instruction Fetch the contents of the memory location pointed to by the PC. The contents of this location are loaded into the IR (fetch phase). IR ← [[PC]] Assuming that the memory is byte addressable, increment the contents of the PC by 4 (fetch phase). PC ← [PC] + 4 Carry out the actions specified by the instruction in the IR (execution phase).
Processor Organization Internal processor bus Control signals PC MDR HAS TWO INPUTS AND TWO OUTPUTS Instruction Address lines decoder and MAR control logic Memory bus MDR Data lines IR Datapath Y R0 Constant 4 Select MUX Add ALU control lines Sub A B Carryin XOR Textbook Page 413 R( n 1 ) ALU TEMP Z Figure 7. 1. Singlebus organization of the datapath inside a processor.