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Note for Microprocessor and Assembly Language Processing - MALP by Neelakantha hss

  • Microprocessor and Assembly Language Processing - MALP
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Unit 7 Input / Output Interfaces Interface is the path for communication between two components. Interfacing is of two types, memory interfacing and I/O interfacing. Memory Interfacing When we are executing any instruction, we need the microprocessor to access the memory for reading instruction codes and the data stored in the memory. For this, both the memory and the microprocessor requires some signals to read from and write to registers. The interfacing process includes some key factors to match with the memory requirements and microprocessor signals. The interfacing circuit therefore should be designed in such a way that it matches the memory signal requirements with the signals of the microprocessor. IO Interfacing There are various communication devices like the keyboard, mouse, printer, etc. So, we need to interface the keyboard and other devices with the microprocessor by using latches and buffers. This type of interfacing is known as I/O interfacing. Block Diagram of Memory & I/O Interfacing 8085 Interfacing Pins Following is the list of 8085 pins used for interfacing with other devices: A15-A8 (Higher Address Bus) AD7-AD0(Lower Address/Data Bus) ALE RD WR READY Ways of Communication − Microprocessor with the Outside World? There are two ways of communication in which the microprocessor can connect with the outside world. Serial Communication Interface: In this type of communication, the interface gets a single byte of data from the microprocessor and sends it bit by bit to the other system serially and vice-a-versa Parallel Communication interface: In this type of communication, the interface gets a byte of data from the microprocessor and sends it bit by bit to the other systems in simultaneous (or) parallel fashion and vice-a-versa. Serial Communication ransmitted at a time. 1

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-232C Modes of serial data transfer i) Simplex mode ii) Half duplex mode ctions but not at the same time. iii) Full duplex mode Types of serial data transfer i) Synchronous It is also called clock-oriented data transmission. ii) Asynchronous -oriented data transmission. Introduction to 8251A PCI (Programmable Communication Interface) The 8251A is a programmable serial communication interface chip designed for synchronous and asynchronous serial data communication. It supports the serial transmission of data. It is packed in a 28 pin DIP. It is also called USART (Universal Synchronous Asynchronous Receiver Transmitter). Fig: Pin Description 2

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Block Diagram: The functional block diagram of 8251A consists of five sections. They are: Read/Write control logic Transmitter Receiver Data bus buffer Modem control. The functional block diagram is shown in fig: Fig: Functional block diagram of 8251A PCI Read/Write control logic: The Read/Write Control logic interfaces the 8251A with CPU, determines the functions of the 8251A according to the control word written into its control register. It monitors the data flow. This section has three registers and they are control register, status register and data buffer. The eight parallel lines, D7-D0, connect to the system data bus so that data words and control/status words can be transferred to and from the device. The chip select (CS) input is connected to an address decoder so the device is enabled when addressed. The signals RD, WR, CS and C/D are used for read/write operations with these three registers. It has two internal addresses, a control address which is selected when C/D is high (1), and a data address which is selected when C/D input is low (0). When the RESET is high, it forces 8251A into the idle mode. The CLK (clock input) is necessary for 8251A for communication with CPU and this clock does not control either the serial transmission or the reception rate. 3

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Transmitter section: The transmitter section accepts parallel data from CPU and converts them into serial data. The transmitter section is double buffered, i.e., it has a buffer register to hold an 8-bit parallel data and another register called output register to convert the parallel data into serial bits. When output register is empty, the data is transferred from buffer to output register. Now the processor can again load another data in buffer register. If buffer register is empty, then TxRDY goes high. If output register is empty then TxEMPTY goes high. The clock signal, TxC controls the rate at which the bits are transmitted by the USART. The clock frequency can be 1, 16 or 64 times the baud rate. Receiver Section: The receiver section accepts serial data and convert them into parallel data The receiver section is double buffered, i.e., it has an input register to receive serial data and convert to parallel, and a buffer register to hold the parallel data. When the RxD line goes low, the control logic assumes it as a START bit, waits for half a bit time and samples the line again. If the line is still low, then the input register accepts the following bits, forms a character and loads it into the buffer register. The CPU reads the parallel data from the buffer register. When the input register loads a parallel data to buffer register, the RxRDY line goes high. The clock signal RxC controls the rate at which bits are received by the USART. During asynchronous mode, the signal SYNDET/BRKDET will indicate the break in the data transmission. During synchronous mode, the signal SYNDET/BRKDET will indicate the reception of synchronous character. MODEM Control: The MODEM control unit allows to interface a MODEM to 8251A and to establish data communication through MODEM over telephone lines. This unit takes care of handshake signals for MODEM interface. Parallel Communication transferred at a time. is complex. Methods of parallel data transfer i) Simple I/O have to do is connect the switch to an I/O port line and read the port. connect the input of the LED buffer on an output port pin and output the logical level required to turn on the light. Fig: Simple I/O 4

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