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Lab Manuals of ECAD by Ashok K

by Ashok K
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Ashok K

Ashok K

VHDL ECAD-Laboratory The students are required to design and draw the internal structure of the following Digital Integrated Circuits and to develop VHDL source code, perform simulation using relevant simulator and analyze the obtained simulation results using necessary synthesizer. Further, it is required to verify the logic with necessary hardware. List of Experiments: 1. Realization of Logic Gates 2. 3 to 8 Decoder- 74138 3. 8*1 Multiplexer-74151 and 2*1 De-multiplexer-74155 4. 4-Bit Comparator-7485. 5. D Flip-Flop- 7474 6. Decade Counter- 7490 7. 4 Bit Counter-7493 8. Shift Register-7495 9. Universal shift register-74194/195 10. Ram (16*4)-74189 (read and write operations) 11. ALU Equipment Required: 1. Xilinix ISE software-latest version 2. Personal computer with necessary pheripherals 3. Hardware kits- Various FPGA families. 1
EXPT. NO : 1 Realization of Logic Gates DATE : 1. AIM: Design Logic gates using VHDL, simulate using ModelSim, Synthesize using Xilinx Synthesis Tool (XST) and Implement using SPARTAN 3 FPGA XC3S400 TQ 144. 2. COMPONENTS & TOOLS REQUIRED: 2.1 XILINX Foundation Series 8.1i, 2.2 Model Sim 6.1, 2.3 Multi Vendor FPGA/CPLD Board, 2.4 PC Pattern generator and Logic Analyzer. 3. THEORY: VHDL supports logical operations like AND, OR, NOR ,NAND, XOR, XNOR,NOT. In this program Logic gates Entity has two inputs A & B and six outputs Y0,Y1……Y6. Logic gates are described using data flow model. Logic Gates 4. VHDL Program: library IEEE; use IEEE.STD_LOGIC_1164.all; entity LGATES is port( A : in STD_LOGIC; B : in STD_LOGIC; Y0 : out STD_LOGIC; Y1 : out STD_LOGIC; Y2 : out STD_LOGIC; Y3 : out STD_LOGIC; Y4 : out STD_LOGIC; Y5 : out STD_LOGIC; Y6 : out STD_LOGIC ); end LGATES; architecture arch_LGATES of LGATES is begin 2
Y0 <= A AND B; Y1 <= A OR B; Y2 <= A NAND B; Y3 <= A NOR B; Y4 <= A XOR B; Y5 <= A XNOR B; Y6 <= NOT A; end arch_LGATES; 5. PROCEDURE: 1. Open Xilinx Project Navigator 2. Open New Project 3. Select Target Device details 4. Enter VHDL Program 5. Compile for Syntax errors 6. Simulate design using Model Sim 7. Verify the functionality of design with expected results and draw input and output waveforms 8. Synthesize design using XST (Xilinx Synthesis Tool) 9. Write User Constrain File to fix in/out ports on Target device 10. Generate programming file 11. Down load design to the target device on FPGA/CPLD FPGA/CPLD demo board 12. Verify the functionality of design with expected results 6. EXPECTED RESULTS: A B Y0= A AND B Y1= A OR B Y2= A NAND B Y3= A NOR B Y4= A XOR B Y5= A XNOR B Y6= NOT A 0 0 1 1 0 1 0 1 0 0 0 1 0 1 1 1 1 1 1 0 1 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 6. CONCLUSION: Logic Gates has been designed using VHDL, simulated using Model Sim, Synthesized using XST (Xilinx Synthesis Tool) and Implemented using SPARTAM 3 XC3S400 TQ 144.Verified with expected results. 3
7. PRECAUTIONS: 1. Select your VHDL File before you simulate using Model Sim and synthesize using XST. 2. Check JTAG cable connections to down load design to the Target device on FPGA/CPLD demo board. 3. Check Your Target Device details to synthesize design. 4. Check Your Target Device details to write UCF file. 5. Handle FPGA/CPLD Board carefully. 8. VIVA -VOCE QUESTIONS: 1. What is VHDL? 2. What are built in Logical Operations in VHDL? 3. Explain what is need for IEEE library? 4. Explain what is need for std_logic_1164 package? 5. What is Entity and Architecture? 6. What is a Simulation and Give different type of Simulations? 7. What is a Synthesis and Give different type of Synthesis? 8. What are different steps involved to Simulate and synthesize the VHDL program in Xilinx? 9. How to create project in Xilinx Founation Series? 4

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