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BPUT Previous Year Question
Digital Electronics Circuit (PCEC4202)
CMOS Logic Circuit
1. Define setup time and propagation delay. [2010]
2. Define Propagation time and switching time of the logic circuits. [2014]
3. What do you mean by output switching times and propagation delay time of the
integrated logic circuits? [2014-S]
4. Explain a simple technique to determine propagation delay of logic gate. [2005]
5. With the help of suitable diagram explain briefly what you understand by propagation
delay in CMOS logic circuits. [2012]
6. What is “Fan in” and “Fan Out” of the integrated logic circuits? [2011],[2013]
7. How Fan out of gate is specified. [2008]
8. Describe in brief the construction, circuit diagram and operations of MOS and CMOS
logic circuits. [2009]
9. Basic construction of MOS, transistor symbol of P-channel transistors and n-channel
transistors and implement of an inverter circuit. [2008]
10. Describe, in brief, the construction circuit diagram and operation of MOS and CMOS
logic circuits. [2014]
11. Write shot note on “C-MOS inverter”. [2013]
12. Draw the layout of CMOS Inverter or NOT gate. [2010], [2011]
13. Construct a single CMOS logic gate that gives an output of the form F x y z
Where x, y and z as direct inputs (not their complement.) [2011], [2014-S]
14. Draw the CMOS circuit and sketch the stick diagram for AOI22 function. [2012]
15. Write any two design rules for MOSFET. [2011]
16. Shot Note on “Floor Plans in VLSI”. [2014-S]
17. What is Lithography Process? [2014-S], [2014]
Or Shot Note on “Lithography and Patterning”. [2010], 2012]

BPUT Previous Year Question
Digital Electronics Circuit (PCEC4202)
Combinational Circuit Design
1. Realize a combinational circuit which produces output 1 when there is even number of ones
in the input. [2013]
2. A majority logic function that is equal to 1 if the majority of the variables are equal to 1,
equal to 0 otherwise. Design a combinational circuit for four bit majority function. [2013]
3. Design a logic circuit that will allow a signal A to pass to the output only when the control
inputs B and C are HIGH, otherwise the output will stay LOW. [2012]
4. Design a logic circuit with input signal A, control input B and outputs X and Y to operate as
follows: [2012]
(i)
When B=1, output X will follow the input A and output Y will be 0.
(ii)
When B=0, output X will be 0 and output Y will follow the input A.
5. Design a combinational circuit that accepts a three bit binary number and generates an output
equal to the square of the input number. [2006-S]
6. What is the characteristics equation of an unknown combinational circuit which has the
following characteristics table? Other conditions may be taken as “don’t care”. Now, realize
the combinational circuit using logic gates. [2014]
Input(X) Input(Y) Input(Z) Output(Q)
0
0
1
1
1
0
1
0
0
1
1
1
1
1
1
1
7. What do you mean by 3-state logic?
What is important in Combinational Circuit? [2008], [2014], [2014-S]
8. Construct a Full adder using half adder. [2006-S]
9. Binary Parallel Adder (Shot Note) [2010],[2014-S]
10. carry look ahead adder (Shot Note) [2013], [2010]
11. Describe the Principle of “Carry” Look-ahead technique. Write the Boolean function and
draw the logic diagram of a 4-bit carry, look-ahead generator. Now construct a 4-bit adder
with carry look ahead. [2008]
12. 2-bit Multiplier (Shot Note) [2011]
13. Draw a circuit diagram of a 2-bit by 2-bit binary multiplier using half adder and logic gates.
Explain its operation. [2009]
14. Design a combinational circuit that compares two 4-bir numbers A and B to check if they are
equal. The circuit has one output f=1,if A=B and f=0 if A≠B. [2006-S]
15. Shot Note on “magnitude comparator”. [2009]
16. Design a 4-bit comparator using gates. [2005]
17. A magnitude comparator is combinational circuit that compares two numbers. A & B and
determine their relative magnitudes. The outcome of the comparison is specified by three

BPUT Previous Year Question
Digital Electronics Circuit (PCEC4202)
binary variables that indicates whether A>B, A=B, or A<B. Determine the algorithm to
implement this comparator and draw a 4 –bit magnitude comparator using combinational
circuit. [2008]
18. Implement the following Boolean function using 4×1 MUX. [2014-S]
F ABC ABC ABC ABC
19. Implement the Boolean function by using 4×1 MUX. [2014]
F AB C ABC AB C ABC
20. Implement a combinational logic circuit described by the following truth table using 4×1
Multiplexer. A, B, C are the inputs and Z is the output. [2011]
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Z
0
1
0
1
1
1
0
1
21. Implement the logic function F(A,B,C,D)=Σm(1,2,4,5,14,15) using 8×1 multiplexer.[2006-S]
22. Realize the expression X A B C A BC AB C A B C with 2:1 MUXs. [2005]
23. Suppose that you need a 3:1 MUX in your system. Discuss how you can implement this
using two 2:1 MUXs and what problem might arise in this application. [2012]
24. Encoder (Shot Note) [2013]
25. What is decoder? How is it differs from demultiplexer? [2006-S]
26. Distinguish between Decoder, Encoder and Multiplexer in digital Circuits. [2009], [2008]
27. Draw a logic diagram of 2×4 decoder with active low enable signal. [2011],[2014-S]
28. Write characteristics equation and table for a full adder circuit. Then implement the full
adder with decoder and NAND gates. [2013]
29. Consider a digital system which will take 3-binary bits as input and the output can be derived
as the square of the binary input. Derive the truth table and implement it with the 3×8
decoder and required basic logic gates. [2010]
30. A Combinational circuit is defined by the following three functions. [2011]
F1 xy xyx
F2 x y xz
F3 xy z
Design the digital system using a suitable decoder and external logic gates.
31. Design a Combinational Circuit that converts a 4-bit Gray Code to a 4-bit binary number.
Implement the circuit using Exclusive-OR gates. [2009]
32. Draw the circuit diagram and truth table of [2008]
(i)
3-bit even parity generator
(ii)
4-bit even parity checker
------------------------------------------******-----------------------------------------------

BPUT Previous Year Question
Digital Electronics Circuit (PCEC4202)
Design and Analysis of Sequential Circuits
1. Write Shot Note on “Importance of State
Machine”. [2014-S]
2. Design a clocked sequential circuit using
D-FF for the state diagram given below.
[2006-S]
3. Construct the state diagram for the
system described in the state table given
below. Note that x is the input and A and
B are the state variables.
[2012]
Present Values
Next State
X(t) A(t)
B(t)
A(t+1) B(t+1)
0
0
0
0
0
0
0
1
1
1
0
1
0
1
0
0
1
1
0
1
1
0
0
1
1
1
1
1
0
1
1
1
0
1
1
0
0
A(t)
0
1
1
0
0
1
1
0
B(t)
0
1
0
0
0
1
0
0
A(t+1)
0
1
1
0
0
1
1
0
7. Draw the State table and state diagram
for the given clocked sequential circuit.
0
1
0
4. Draw the state diagram for the state table
shown below. Note that A, B are two
state variable and C is the input. [2014-S]
C(t)
0
0
0
0
1
1
1
1
5. Design a state machine using D-flip-flop
that cycles through 4 states, and generate
a logic’1’ on a output named “beep”
during the last state (and generate a logic
‘0’ on that output otherwise). Show your
state encoding and the Karnaugh Maps
for generating the next state logic and
the output. [2012]
6. Consider the sequential circuit shown in
the Figure below. In this circuit P is the
input and f is the output, and A is the
state variable. Construct the state table
of the circuit. [2012]
B(t+1)
0
1
0
1
0
1
0
1
8. Analyze the clocked synchronous state
machine shown in figure below. Write
the
excitation
equations,
excitation/transition
table
and
state/output table(use state names A-D
for Q1Q2= 00- 11) [2012]

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