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Note for VHDL Programming - VHDL by sravya jayanthi

  • VHDL Programming - VHDL
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Why Use an HDL ? • Hard to design directly for complex systems • Formal description using HDL – Verify the specification through simulation or verification – Easy to change – Enable automatic synthesis • • • • Allow architectural tradeoffs with short turnaround Reduce time for design capture Encourage focus on functionality Shorten the design verification loop *HDL = Hardware Description Language 2-3 Hardware Description Language • Have high-level language constructs to describe the functionality and connectivity of the circuit • Can describe a design at some levels of abstraction – Behavioral, RTL, Gate-level, Switch • Can describe functionality as well as timing • Can be used to model the concurrent actions in real hardware • Can be used to document the complete system design tasks – testing, simulation … related activities • Comprehensive and easy to learn 2-4 2

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Verilog History • Gateway Design Automation – Phil Moorbr in 1984 and 1985 • Verilog-XL, “XL algorithm”, 1986 – Fast gate-level simulation • Verilog logic synthesizer, Synopsys, 1988 – Top-down design methodology • Cadence Design Systems acquired Gateway, 1989 – A proprietary HDL • Open Verilog International (OVI), 1991 – Language Reference Manual (LRM) • The IEEE 1364 working group, 1994 • Verilog became an IEEE standard – December, 1995 2-5 What is Verilog HDL ? • Hardware description language • Mixed level modeling gate – Behavioral • Algorithmic • Register transfer algo – Structural • Gate • Switch • Single language for design and simulation • Built-in primitives and logic functions • User-defined primitives • Built-in data types • High-level programming constructs RTL switch gate 2-6 3

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Books • Palnitkar S.,” Verilog HDL: A Guide to Digital Design and Synthesis”, Prentice Hall, NJ, 1996. (ISBN: 0-13-451675-3) • Thomas D. and P. Moorby, “The Verilog Hardware Description Language”, Kluwer Academic, MA, 1991. (ISBN: 0-7923-9126-8) • Sternheim E., E. Singh, and Y. Trivedi, “Digital Design with Verilog HDL”, Automata Publishing Company, CA, 1990. (ISBN: 0-9627488-0-3) Official Language Document: • “Verilog Hardware Description Language Reference Manual”, IEEE Std 1364-1995, IEEE. 2-7 Outline • Introduction • Language elements – Modules – Lexical conventions – Data types • • • • • Gate-level modeling Data-flow modeling Behavioral modeling Other topics Simulation and test bench 2-8 4

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Basic Unit -- Module • Modules communicate externally with input, output and bi-directional ports • A module can be instantiated in another module module module_name (port_list); declarations: port declaration (input, output, inout, …) data type declaration (reg, wire, parameter, …) task and function declaration statements: initial block Behavioral always block module instantiation Structural gate instantiation UDP instantiation continuous assignment Data-flow endmodule module statements ports 2-9 An Example module FA_MIX (A, B, CIN, SUM, COUT); input A,B,CIN; output SUM, COUT; reg COUT; reg T1, T2, T3; wire S1; xor X1 (S1, A, B); // Gate instantiation. always @ (A or B or CIN) // Always Block begin T1 = A & CIN; T2 = B & CIN; T3 = A & B; COUT = (T1 | T2 | T3); END assign SUM = S1 ^ CIN; // Continuous assignment endmodule 2-10 5

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