It does not matter how slowly you go as long as you do not stop.
--Your friends at LectureNotes

Note for Analog Electronic Circuits - AEC By Divyansh Das

  • Analog Electronic Circuits - AEC
  • Note
  • 8 Topics
  • 1 Offline Downloads
  • Uploaded 11 months ago
0 User(s)
Download PDFOrder Printed Copy

Share it with your friends

Leave your Comments

Text from page-2

Chapter 1 FIELD EFFECT TRANSISTORS 1.1 INTRODUCTION The field-effect transistor (FET) is a three-terminal device used for a variety of applications that match, to a large extent. Although there are important differences between the two types of devices, there are also many similarities. The primary difference between the two types of transistors is the fact that the BJT transistor is a current-controlled device as depicted in Fig. 1.1(a), while the JFET transistor is a voltage-controlled device as shown in Fig. 1.1(b). In other words, the current IC in Fig. 1.1(a) is a direct function of the level of IB. For the FET the current I will be a function of the voltage VGS applied to the input circuit as shown in Fig. 1.1(b). Fig. 1.1 (a) Current-controlled and (b) voltage-controlled amplifiers In each case the current of the output circuit is being controlled by a parameter of the input circuit—in one case a current level and in the other an applied voltage. Just as there are npn and pnp bipolar transistors, there are n-channel and p-channel field-effect transistors. However, it is important to keep in mind that the BJT transistor is a bipolar device—the prefix bi- revealing that the conduction level is a function of two charge carriers, electrons and holes. The FET is a unipolar device depending solely on either electron (n-channel) or hole (p-channel) conduction. The term field-effect in the chosen name deserves some explanation. For the FET an electric field is established by the charges present that will control the conduction path of the output circuit without the need for direct contact between the controlling and controlled quantities. Page | 2

Text from page-3

One of the most important characteristics of the FET is its high input impedance. At a level of 1 to several hundred mega ohms it far exceeds the typical input resistance levels of the BJT transistor configurations—a very important characteristic in the design of linear ac amplifier systems. On the other hand, the BJT transistor has a much higher sensitivity to changes in the applied signal. In other words, the variation in output current is typically a great deal more for BJTs than FETs for the same change in applied voltage. For this reason, typical ac voltage gains for BJT amplifiers are a great deal more than for FETs. In general, FETs are more temperature stable than BJTs, and FETs are usually smaller in construction than BJTs, making them particularly useful in integrated-circuit (IC) chips. The construction characteristics of some FETs, however, can make them more sensitive to handling than BJTs. Two types of FETs are there: the junction field-effect transistor (JFET) and the metal-oxide-semiconductor field-effect transistor (MOSFET). The MOSFET category is further broken down into depletion and enhancement types. The MOSFET transistor has become one of the most important devices used in the design and construction of integrated circuits for digital computers. Its thermal stability and other general characteristics make it extremely popular in computer circuit design. 1.2 CONSTRUCTION AND CHARACTERISTICS OF JFETs The JFET is a three-terminal device with one terminal capable of controlling the current between the other two. The basic construction of the n-channel JFET is shown in Fig. 1.2. Note that the major part of the structure is the n-type material that forms the channel between the embedded layers of p-type material. The top of the n-type channel is connected through an ohmic contact to a terminal referred to as the drain (D), while the lower end of the same material is connected through an ohmic contact to a terminal referred to as the source (S). The two p-type materials are connected together and to the gate (G) terminal. In essence, therefore, the drain and source are connected to the ends of the n-type channel and the gate to the two layers of p-type material. In the absence of any applied potentials the JFET has two p-n junctions under no-bias conditions. The result is a depletion region at each junction as shown in Fig. 1.2 that resembles the same region of a diode under no-bias conditions. A depletion region is that region void of free carriers and therefore unable to support conduction through the region. The drain and source terminals are at opposite ends of the n-channel as introduced in Fig. 1.2 because the terminology is defined for electron flow. Page | 3

Text from page-4

Fig 1.2 Junction field-effect transistor (JFET) VGS = 0 V, VDS Some Positive Value In Fig. 1.3, a positive voltage VDS has been applied across the channel and the gate has been connected directly to the source to establish the condition VGS = 0 V. The result is a gate and source terminal at the same potential and a depletion region in the low end of each p-material similar to the distribution of the no-bias conditions of Fig. 1.2. The instant the voltage VDD (= VDS) is applied, the electrons will be drawn to the drain terminal, establishing the conventional current ID with the defined direction of Fig. 1.3. The path of charge flow clearly reveals that the drain and source currents are equivalent (ID = IS). Under the conditions appearing in Fig. 1.3, the flow of charge is relatively uninhibited and limited solely by the resistance of the n-channel between drain and source. Fig 1.3 JFET in the VGS = 0 V and VDS > 0 V Page | 4

Text from page-5

As the voltage VDS is increased from 0 to a few volts, the current will increase as determined by Ohm’s law and the plot of ID versus VDS will appear as shown in Fig. 1.4. The relative straightness of the plot reveals that for the region of low values of VDS, the resistance is essentially constant. As VDS increases and approaches a level referred to as VP in Fig. 1.4, the depletion regions of Fig. 1.3 will widen, causing a noticeable reduction in the channel width. The reduced path of conduction causes the resistance to increase and the curve in the graph of Fig. 1.4 to occur. The more horizontal the curve, the higher the resistance, suggesting that the resistance is approaching “infinite” ohms in the horizontal region. Fig 1.4 ID versus VDS for VGS=0 V If VDS is increased to a level where it appears that the two depletion regions would “touch” as shown in Fig. 1.5, a condition referred to as pinch-off will result. The level of VDS that establishes this condition is referred to as the pinchoff voltage and is denoted by VP as shown in Fig. 1.4. In actuality, the term pinch-off suggests the current ID is pinched off and drops to 0 A. As shown in Fig. 1.4, ID maintains a saturation level defined as IDSS. In reality a very small channel still exists, with a current of very high density. The fact that ID does not drop off at pinch-off and maintains the saturation level indicated in Fig. 1.4 is verified by the following fact: The absence of a drain current would remove the possibility of different potential levels through the n-channel material to establish the varying levels of reverse bias along the p-n junction. The result would be a loss of the depletion region distribution that caused pinch-off in the first place. Page | 5

Lecture Notes