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Note of fabrication by Minakshi Das

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See discussions, stats, and author profiles for this publication at: https://www.researchgate.net/publication/261567038 Design and fabrication of 2.4 GHz pre-biased rectifier Article in Analog Integrated Circuits and Signal Processing · May 2014 DOI: 10.1007/s10470-014-0256-6 CITATIONS READS 0 343 4 authors, including: Masayuki Ikebe E. Sano Hokkaido University Hokkaido University 94 PUBLICATIONS 207 CITATIONS 242 PUBLICATIONS 3,049 CITATIONS SEE PROFILE All content following this page was uploaded by E. Sano on 30 September 2015. The user has requested enhancement of the downloaded file. SEE PROFILE

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Design and fabrication of 2.4 GHz pre-biased rectifier Yutaro Otsu†, Keishi Kubo†, Masayuki Ikebe*, and Eiichi Sano† †Research Center for Integrated Quantum Electronics, Hokkaido University, Sapporo 060–8628 Japan *Graduate School of Information Science and Technology, Hokkaido University, Sapporo 060–0814 Japan Tel: +81-11-706-6874, Fax: +81-11-706-6004 E-mail: esano@rciqe.hokudai.ac.jp Abstract—A 2.4 GHz rectifier operating in a region of low RF input power was developed. The rectifier has a cross-coupled bridge configuration and is driven by a differential RF input signal. Since a rectifier needs an RF signal higher than the threshold voltage of transistors, we introduced a pre-biasing circuit to compensate for the threshold voltage. A low-voltage digital circuit, subthreshold voltage regulator, and lowpower level shifter were introduced for reducing the power consumption of the pre-biasing circuit and increasing the driving voltage for the switches at the same time. The circuit simulations revealed that the pre-biasing circuit was effective in a low RF input power region. However, the output voltage was degraded in a high power region. Then, we combined the pre-biased rectifier in parallel with a non-biased rectifier. Three types of rectifiers consisting of LC matching circuits, 3-stage rectifier cells, and biasing circuits were designed and fabricated using a 0.18-μm mixed signal/RF CMOS process with one poly and six metal layers. The fabricated pre-biased rectifier operated in a region of RF input power of less than -15 dBm, while the non-biased rectifier could not operate in this region. The parallel combination of pre-biased and non-biased rectifiers effectively solved the drawback of the pre-biased rectifier in a high RF input power region. Keywords: rectifier, sensor network, 2.4 GHz, RF, low-power pulse generator, subthreshold CMOS 1

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1. Introduction Recently, wireless sensor networks (WSNs) and radio frequency identification (RFID) tags have attracted much attention towards the realization of a ubiquitous network society. A wireless sensor node consists of a sensor, analog-to-digital converter, digital signal processor, and wireless transceiver. Much work has been done for achieving small, low cost, and low power consumption sensor nodes. The power consumption of the node is one of the most crucial problems to be solved because individual node battery replacement is impractical due to deployment of many nodes and/or inaccessible nodes [1-3]. An ideal solution is to operate wireless sensor nodes with electric energy converted from solar, thermal, and vibration energy in the environment. In the meantime, however, such energy harvesting technology is limited to only specific applications. A realistic solution is a combination of a rechargeable battery and energy harvesting for extending the battery lifetime [4]. RF power feeding from base stations where the RF signal is converted to DC power with a rectifier is an attractive method [1, 2]. Schottky diodes have been used for achieving highly efficient rectifiers [5]. Since Schottky diodes cannot be fabricated using the standard CMOS process and the other circuits in a sensor node are fabricated using the CMOS process, a diode should be made by connecting the gate and drain of a MOS transistor. The most critical problem in the diode-connected MOS transistor is a drastic reduction in the conversion efficiency when the amplitude of the input RF signal is less than the threshold voltage Vth of the transistor. Several methods have been devised for solving this problem. Yao et al. used transistors with ultralow Vth in 0.35-m CMOS process [6], while Le et al. reduced Vth by injecting the charge via Fowler-Nordheim tunneling [1]. However, these methods are not available in the standard CMOS process. Vth cancelling with self-biasing [2, 7, 8] and external biasing [9] simply and effectively increase the conversion efficiency. Despite those efforts, the minimum detectable RF input power of around -20 dBm is still high. A rectifier can also be used as an envelope detector in a wake-up receiver. However, the sensitivity of the detector [10] is quite low compared with other wake-up receivers [3]. In this paper, we propose a pre-biased rectifier to improve the minimum detectable RF input power based on the differential-drive CMOS rectifier [8]. A carrier frequency of 2.4 GHz is used here because a small antenna of 2 cm can be used in this frequency region [11]. 2. Circuit configuration As mentioned in the previous section, the DC output voltage degrades drastically when the peak voltage of the input RF signal is less than the threshold voltage Vth of the MOSFET. To solve this problem, we used a pre-biasing technique with the differential-drive CMOS rectifier proposed by Kotani et al. [8]. In principle, the pre-biasing circuit operates with the energy generated by the rectifier itself. In this paper, however, an external voltage source was used to drive the pre-biasing circuit for simplifying the proof of the concept. 2

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2.1 Basic rectifier cell Figure 1(a) shows the basic cell of the differential-drive CMOS rectifier proposed by Kotani et al. [8]. The input node DCin was grounded for operating the basic cell as a one-stage rectifier. When RF+ was positive and RF- was negative, the on-resistances of pMOS MP1 and nMOS MN2 were low while those of MP2 and MN1 were high. On the other hand, when RF+ was negative and RF- was positive, the on-resistances of MP1 and MN2 were high while those of MP2 and MN1 were low. As these two states were repeated, the potential of DCout gradually increased. At the same time, the average potential of V1 and V2 were almost the same as half the potential of DCout, which effectively compensated the Vth of the transistors. To improve the minimum detectable RF input power, we introduce a pre-biasing circuit into a modified version of the original rectifier. Figures 1(b) and 1(c) show the basic cell of our pre-biased rectifier and the pulse waveform driving the switches. For simplifying the biasing scheme, only nMOS’s were used instead of the original CMOS configuration. At the start, the switches SW1 and SW1’ were closed while SW2 and SW2’ were open. In this period, the gate nodes of the transistors were charged. Rectifying started by turning off SW1 and SW1’ and turning on SW2 and SW2’. The on-resistances of SW2 and SW2’ should be low enough to lower the RF signal loss. Note that the RF input signal was not rectified during the gate charging period. Therefore, the gate charging period should be as short as possible. In addition, the power consumption of the pulse generator for controlling the switches should be as low as possible. 2.2 Pulse generator A low duty cycle, low power consumption, and high driving voltage for the switches were required for the pulse generator. The block diagram of the pulse generator is shown in Fig. 2. A driving voltage of 1.5 V was used to reduce the on-resistances of the switches, while low-voltage digital circuits were introduced to reduce the power consumption as well as the duty cycle of the pulse. A voltage regulator was used to generate the supply voltage VDDL of 0.5 V for the digital circuits. A pulse train was generated with NAND operation of two outputs from two successive inverter stages in a 9-stage ring oscillator, as shown in Fig. 2. The level shifter increased the pulse amplitude from 0.5 V to 1.5 V. Figure 3 shows the circuit diagram for the voltage regulator. The voltage VDDL was kept the same as the gate voltage of M1,Vref, generated with a pMOS ladder circuit. To reduce the power consumption, a subthreshold op-amp was used [12]. In the op-amp, the gate of the current source M2 was grounded, and the operating current was controlled by changing the gate width of M2. The supply voltage VDDL might deviate from the designed value due to Vth variations of the MOSFETs. Since precise control of the period of the pulses was not needed, this deviation was not significant. 3

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