S. S. EDUCATION TRUST (R) S. G. BALEKUNDRI INSTITUTE OF TECHNOLOGY SHIVABASAV NAGAR BELAGAVI-10 DSP ALGORITHMS AND ARCHITECTURE [10EC751] Notes as per VTU Syllabus for VII Semester Electronics & Communication Engineering Mr. Sunil S Harakannanavar BE,M.tech (Control Systems) Assistant Professor Department Of Electronics & Communication Engineering S G Balekundri Institute Of Technology, Belagavi-10 Email: firstname.lastname@example.org Mobile: 7411844948
DSP ALGORITHMS AND ARCHITECTURE SEMESTER – VII (E&CE) 10EC751 IA Marks 04 Exam Hours 52 Exam Marks Subject Code Number of Lecture Hours/Week Total Number of Lecture Hours Course objectives: This course will enable students to: 25 03 100 To understand the sampling concept, DFT and FFT, Digital Filters, and the concept of Interpolation and Decimation. To understand the basic architectural features of programmable processors, Bus Architecture and memory organization. To understand data modes of TMS32054xx families, and how the program control occurs in TMS32054xx processors. To discuss the total Instruction sets of TMS320C54x and TMS32OC54xx Processor, and how programming is performed in both processor families. Design Interpolation and decimation filters, and Comparison of FIR Filters with IIR Filters. To understand how memory is organized in overall connecting peripherals to the DSP devices and the role of Interrupts. To study the Image processing system and design of a CODEC Interface Circuit. CHAPTERS Teaching Hours (RBT)Level 06 Hours L1, L2, L3 07 Hours L1, L2, L3 06 Hours L1, L2, L3 07 Hours L1, L2, L3 07 Hours L1, L2, L3 06 Hours L1, L2, L3 CHAPTER 1 INTRODUCTION TO DIGITAL SIGNAL PROCESSING: Introduction, A Digital Signal-Processing System, The Sampling Process, Discrete Time Sequences, Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT), Linear TimeInvariant Systems, Digital Filters, Decimation and Interpolation. CHAPTER 2 Introduction, Basic Architectural Features, DSP Computational Building Blocks, Bus Architecture and Memory, Data Addressing Capabilities, Address Generation Unit, Programmability and Program Execution, Features for External Interfacing. CHAPTER 3 PROGRAMMABLE DIGITAL SIGNAL PROCESSORS: Introduction, Commercial Digital Signal-processing Devices, Data Addressing Modes of TMS32OC54xx., Memory Space of TMS32OC54xx Processors, Program Control. CHAPTER 4 Detail Study of TMS320C54X & 54xx Instructions and Programming: On Chip peripherals, interrupts of TMS32OC54XX Processors, Pipeline Operation of TMS32OC54xx Processor. CHAPTER 5 IMPLEMENTATION OF BASIC DSP ALGORITHMS: Introduction, the Qnotation, FIR Filters, IIR Filters, Interpolation and Decimation Filters (one example in each case). CHAPTER 6 IMPLEMENTATION OF FFT ALGORITHMS: Introduction, An FFT Algorithm for DFT Computation, Overflow and Scaling, Bit-Reversed Index Generation & Implementation on the TMS32OC54xx.
CHAPTER 7 INTERFACING MEMORY AND PARALLEL I/O PERIPHERALS TO DSP DEVICES: Introduction, Memory Space Organization, External Bus Interfacing Signals. Memory Interface, Parallel I/O Interface, Programmed I/O, Interrupts and I / O Direct Memory Access (DMA). 06 Hours L1, L2, L3 07 Hours L1, L2, L3 CHAPTER 8 INTERFACING AND APPLICATIONS OF DSP PROCESSOR: Introduction, Synchronous Serial Interface, A CODEC Interface Circuit. DSP Based Biotelemetry Receiver, A Speech Processing System, An Image Processing System. Course Outcomes: At the end of the course, students will be able to: Understand how the program control occurs in TMS32054xx processors. The Digital Filters and the concept of Interpolation and Decimation, the total Instruction sets of TMS320C54x and TMS32OC54xx Processor. Understand how memory is organized in overall connecting peripherals to the DSP devices. Design algorithms for DFT Computations. Understand the application and advantages of the DSP based Bio-telemetry Receiver, Speech processing system and Image processing system. Graduating Attributes (as per NBA) Engineering Knowledge Problem Analysis Design / development of solutions (partly) Text Book: 1) “Digital Signal Processing”, Avatar Singh and S. Srinivasan, Thomson Learning, 2004. Reference Books: 1. Digital Signal Processing: A practical approach, Ifeachor E. C., Jervis B. W Pearson-Education, PHI/ 2002. 2. “Digital Signal Processors”, B Venkataramani and M Bhaskar TMH, 2nd, 2010 3. “Architectures for Digital Signal Processing”, Peter Pirsch John Weily, 2008
INDEX SL.NO CHAPTER CONTENTS PAGE NO. 1 2 3 5 6 7 UNIT-1 UNIT-2 UNIT-3 UNIT-5 UNIT-6 UNIT-7 INTRODUCTION TO DIGITAL SIGNAL PROCESSING: A Digital Signal-Processing System The Sampling Process Discrete Time Sequences Discrete Fourier Transform (DFT) Fast Fourier Transform (FFT) Linear Time-Invariant Systems Digital Filters Decimation and Interpolation 1-1 1-2 3-3 3-5 6-7 8-9 9-10 11-13 13-15 ARCHITECTURES FOR PROGRAMMABLE SIGNAL PROCESSORS : Introduction Basic Architectural Features DSP Computational Building Blocks Bus Architecture and Memory Data Addressing Capabilities Address Generation Unit Programmability and Program Execution Features for External Interfacing 19-19 DIGITAL 19-20 21-33 33-36 37-40 41-42 42-45 46-46 PROGRAMMABLE DIGITAL SIGNAL PROCESSORS: Commercial Digital Signal-processing Devices Data Addressing Modes of TMS32OC54xx Memory Space of TMS32OC54xx Processors Program Control 47-47 47-56 57-65 65-68 69-69 IMPLEMENTATION OF BASIC DSP ALGORITHMS: Q-notation FIR Filters IIR Filters Interpolation and Decimation Filters (one example in each case). 70-70 70-73 74-78 78-80 81-87 IMPLEMENTATION OF FFT ALGORITHMS: Introduction An FFT Algorithm for DFT Computation Overflow and Scaling Bit-Reversed Index Generation Implementation on the TMS32OC54xx 88-88 88-93 94-96 96-97 97-101 INTERFACING MEMORY AND PARALLEL PERIPHERALS TO DSP DEVICES: Introduction Memory Space Organization External Bus Interfacing Signals Memory Interface Parallel I/O Interface Programmed I/O Interrupts I / O Direct Memory Access (DMA) I/O 102-102 102-105 106-109 110-110 110-111 112-113 114-117