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**Jawaharlal Nehru Technological University Anantapur (JNTU) College of Engineering (CEP), Pulivendula, Pulivendula, Andhra Pradesh, India - JNTUACEP**- Computer Science Engineering
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Course Material (Lecture Notes) CS6303 – COMPUTER ARCHITECTURE LESSION NOTES UNIT II ARITHMETIC OPERATIONS ALU In computing an arithmetic logic unit (ALU) is a digital circuit that performs arithmetic and logical operations. The ALU is a fundamental building block of the central processing unit (CPU) of a computer, and even the simplest microprocessors contain one for purposes such as maintaining timers. The processors found inside modern CPUs and graphics processing units (GPUs) accommodate very powerful and very complex ALUs; a single component may contain a number of ALUs. Mathematician John von Neumann proposed the ALU concept in 1945, when he wrote a report on the foundations for a new computer called the EDVAC. Research into ALUs remains an important part of computer science, falling under Arithmetic and logic structures in the ACM Computing Classification System FIXED POINT NUMBER AND OPERATION In computing, a fixed-point number representation is a real data type for a number that has a fixed number of digits after (and sometimes also before) the radix point (e.g., after the decimal point '.' in English decimal notation). Fixed-point number representation can be compared to the more complicated (and more computationally demanding) floating point number representation. CS6303 – COMPUTER ARCHITECTURE UNIT-II Page 1

Course Material (Lecture Notes) Fixed-point numbers are useful for representing fractional values, usually in base 2 or base 10, when the executing processor has no floating point unit (FPU) or if fixed-point provides improved performance or accuracy for the application at hand. Most low-cost embedded microprocessors and microcontrollers do not have an FPU. FLOATING POINT NUMBERS & OPERATIONS Floating point Representation: To represent the fractional binary numbers, it is necessary to consider binary point.If binary point is assumed to the right of the sign bit ,we can represent the fractional binary numbers as given below, Direct implementation of dedicated units : always : 1 – 5 in most cases : 6 sometimes : 7, 8 Sequential implementation using simpler units and several clock cycles (_decomposition) : sometimes : 6 in most cases : 7, 8, 9 Table lookup techniques using ROMs : universal : simple application to all operations efficient only for singleoperand operations of high complexity (8 – 12) and small word length (note: ROM size Approximation techniques using simpler units : 7–12 �taylor series expansion �polynomial and rational approximations �convergence of recursive equation systems Binary adder This is also called Ripple Carry Adder, because of the construction with full adders are connected in cascade. CS6303 – COMPUTER ARCHITECTURE UNIT-II Page 2

Course Material (Lecture Notes) Carry Look Ahead Adder The most widely used technique employs the principle of carry look-ahead to improve the speed of the algorithm. Binary subtractor Usually there are more bits in the partial products and it is necessary to use full adders to produce the sum of the partial products. For J multiplier bits and K multiplicand bits we need (J X K) AND gates and (J − 1) Kbit adders to produce a product of J+K bits. K=4 and J=3, we need 12 AND gates and two 4-bit adders. ALU stands for: Arithmetic Logic Unit ALU is a digital circuit that performs Arithmetic (Add, Sub, . . .) and Logical (AND, OR, NOT) operations. John Von Neumann proposed the ALU in 1945 when he was working on EDVAC Typical Schematic Symbol of an ALU 1-Bit ALU This is an one-bit ALU which can do Logical AND and Logical OR operation. Result = a AND b when operation = 0 Result = a OR b when operation = 1 The operation line is the input of a MUX CS6303 – COMPUTER ARCHITECTURE UNIT-II Page 3

Course Material (Lecture Notes) 32-Bit ALU ADDITION AND SUBTRACTION Addition Half Adder: A combinational circuit that performs the addition of two bits is called a half adder. CS6303 – COMPUTER ARCHITECTURE UNIT-II Page 4

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