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  • Jawaharlal Nehru Technological University Anantapur (JNTU) College of Engineering (CEP), Pulivendula, Pulivendula, Andhra Pradesh, India - JNTUACEP
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UNIT - 1 SYLLABUS: INTRODUCTION TO VERILOG: Verilog as HDL, Levels of design Description, Concurrency, Simulation and Synthesis, Functional Verification, System Tasks, Programming Language Interface (PLI), Module, Simulation and Synthesis Tools, Test Benches. LANGUAGE CONSTRUCTS AND CONVENTIONS: Introduction, Keywords, Identifiers, White Space Characters, Comments, Numbers, Strings, Logic Values, Strengths, Data Types, Scalars and Vectors, Parameters, Operators. -------------------------------------------------------------------------------------------------------------------------------- INTRODUCTION TO VERILOG: VERILOG AS AN HDL Verilog aimed at providing a functionally tested and a verified design description for the target FPGA or ASIC. The language has a dual function – one fulfilling the need for a design description and the other fulfilling the need for verifying the design for functionality and timing constraints like propagation delay, critical path delay, slack, setup, and hold times LEVELS OF DESIGN DESCRIPTION 1. Circuit Level: At the circuit level, a switch is the basic element with which digital circuits are built. Switches can be combined to form inverters and other gates at the next higher level of abstraction. Verilog has the basic MOS switches built into its constructs, which can be used to build basic circuits like inverters, basic logic gates, simple 1-bit dynamic and static memories 2|Page 2

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2. Gate Level :At the next higher level of abstraction, design is carried out in terms of basic gates. All the basic gates are available as ready modules called ―Primitives.‖ Each such primitive is defined in terms of its inputs and outputs. Primitives can be incorporated into design descriptions directly. 3. Data Flow :Data flow is the next higher level of abstraction. All possible operations on signals and variables are represented here in terms of assignments. All logic and algebraic operations are accommodated. The assignments define the continuous functioning of the concerned block. At the data flow level, signals are assigned through the data manipulating equations. All such assignments are concurrent in nature. The design descriptions are more compact than those at the gate level. 4. Behavioral Level :Behavioral level constitutes the highest level of design description; it is essentially at the system level itself. With the assignment possibilities, looping constructs and conditional branching possible, the design description essentially looks like a ―C‖ program. CONCURRENCY In an electronic circuit all the units are to be active and functioning concurrently. The voltages and currents in the different elements in the circuit can change simultaneously. In turn the logic levels too can change. Simulation of such a circuit in an HDL calls for concurrency of operation. Verilog simulators are built to simulate concurrency. SIMULATION AND SYNTHESIS The design that is specified and entered as described is simulated for functionality and fully debugged. Translation of the debugged design into the corresponding hardware circuit (using an FPGA or an ASIC) is called ―synthesis‖. The circuits realized from them are essentially direct translations of functions into circuit elements. FUNCTIONAL VERIFICATION Testing is an essential ingredient of the VLSI design process as with any hardware circuit. It has two dimensions to it – functional tests and timing tests. Testing or functional verification is carried out by setting up a ―test bench‖ for the design. The test bench will have the design instantiated in it; it will generate necessary test signals and apply them to the instantiated design. 3|Page 3

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Test Inputs for Test Benches: Any digital system has to carry out a number of activities in a defined manner. Once a proper design is done, it has to be tested for all its functional aspects. Test inputs can be purely combinational, periodic, numeric sequences, random inputs, conditional inputs, or combinations of these. As the circuit design proceeds, one develops smaller blocks and groups them together to form bigger circuit units. The process is repeated until the whole system is fully built up. Every stage calls for tests to see whether the subsystem at that layer behaves in the manner expected. Such testing calls for two types of observations: Study of signals within a small unit when test inputs are given to the whole unit. Isolation of a small element and doing local test to facilitate debugging. Constructs for Modeling Timing Delays: Any basic gate has propagation delays and transmission delays associated with it. As the elements in the circuit increase in number, the type and variety of such delays increase rapidly; often one reaches a stage where the expected function is not realized thanks to an unduly large time delay. Verilog has constructs for modeling the following delays: Gate delay Net delay Path delay Pin-to-pin delay A design can be tested for setup time, hold time, clock-width time specifications, etc. Such constructs or delay models are akin to the finite delay time, rise time, fall time, path or propagation delays, etc., associated with real digital circuits or systems. The use of such constructs in the design helps simulate realistic conditions in a digital circuit. SYSTEM TASKS A number of system tasks are available in Verilog. Though used in a design description, they are not part of it. Some tasks facilitate control and flow of the testing process. Reading data from specified files into a module and writing back into files are also possible through other tasks. Timescale can be changed prior to simulation with the help of specific tasks for the purpose. A set of system functions add to the flexibility of test benches: They are of three categories: Functions that keep track of the progress of simulation time Functions to convert data or values of variables from one format to another Functions to generate random numbers with specific distributions PROGRAMMING LANGUAGE INTERFACE (PLI) PLI provides an active interface to a compiled Verilog module. The interface adds a new dimension to working with Verilog routines from a C platform. The key functions of the interface are as follows: One can read data from a file and pass it to a Verilog module as input. Such data can be test vectors or other input data to the module. Similarly, variables in Verilog modules can be accessed and their values written to output devices. Delay values, logic values, etc., within a module can be accessed and altered. Blocks written in C language can be linked to Verilog modules. 4|Page 4

Lecture Notes