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DIGITAL DESIGN THROUGH VERILOG HDL

by Jntu Heroes
Type: NoteInstitute: Jawaharlal nehru technological university anantapur college of engineering Specialization: Electronics and Communication EngineeringOffline Downloads: 8Views: 517Uploaded: 9 months agoAdd to Favourite

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DIGITAL DESIGN THROUGH VERILOG HDL by Jntu Heroes

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Introduction to Digital Design Using Digilent FPGA Boards ─ Block Diagram / Verilog Examples Table of Contents Introduction – Digital Design Using FPGAs 1 Example 1 – Switches and LEDs 6 Example 2 – 2-Input Gates 11 Example 3 – Multiple-Input Gates 15 Example 4 – Equality Detector 20 Example 5 – 2-to-1 Multiplexer 22 Example 6 – Quad 2-to-1 Multiplexer 25 Example 7 – 4-to-1 Multiplexer 30 Example 8 – Clocks and Counters 37 Example 9 – 7-Segment Decoder 42 Example 10 – 7-Segment Displays: x7seg and x7segb 47 Example 11 – 2's Complement 4-Bit Saturator 55 Example 12 – Full Adder 60 Example 13 – 4-Bit Adder 65 Example 14 – N-Bit Adder 68 Example 15 – N-Bit Comparator 70 Example 16 – Edge-Triggered D Flip-Flop Available only in print vesion Example 17 – D Flip-Flops in Verilog Example 18 – Divide-by-2 Counter Example 19 – Registers Example 20 – N-Bit Register in Verilog Example 21 – Shift Registers Example 22 – Ring Counters Example 23 – Johnson Counters Example 24 – Debounce Pushbuttons Example 25 – Clock Pulse Example 26 – Arbitrary Waveform Example 27 – Pulse-Width Modulation (PWM) Example 28 – Controlling Position of a Servo Example 29 – Scrolling the 7-Segment Display Example 30 – Fibonacci Sequence iv
Appendix A – Aldec Active-HDL Tutorial Part 1: Project Setup Part 2: Design Entry – sw2led.bde Part 3: Synthesis and Implementation Part 4: Program FPGA Board Part 5: Design Entry – gates2.bde Part 6: Simulation Part 7: Design Entry – HDE Part 8: Simulation – gates2 Appendix B – Number Systems B.1 Counting in Binary and Hexadecimal B.2 Positional Notation B.3 Fractional Numbers B.4 Number System Conversions B.5 Negative Numbers 109 109 113 116 120 122 128 132 135 Available only in print vesion Appendix C – Basic Logic Gates C.1 Truth Tables and Logic Equations C.2 Positive and Negative Logic: De Morgan’s Theorem C.3 Sum of Products Design C.4 Product of Sums Design Appendix D – Boolean Algebra and Logic Equations D.1 Boolean Theorems D.2 Karnaugh Maps Appendix E – Verilog Quick Reference Guide v 175
Introduction 1 Introduction Digital Design Using FPGAs The first integrated circuits that were developed in the early 1960s contained less that 100 transistors on a chip and are called small-scale integrated (SSI) circuits. Medium-scale integrated (MSI) circuits, developed in the late 1960s, contain up to several hundreds of transistors on a chip. By the mid 1970s large-scale integrated (LSI) circuits containing several thousands of transistors had been developed. Very-large-scale integrated (VLSI) circuits containing over 100,000 transistors had been developed by the early 1980s. This trend has continued to the present day with 1,000,000 transistors on a chip by the late 1980s, 10,000,000 transistors on a chip by the mid-1990s, over 100,000,000 transistors by 2004, and up to 1,000,000,000 transistors on a chip today. This exponential growth in the amount of digital logic that can be packed into a single chip has produced serious problems for the digital designer. How can an engineer, or even a team of engineers, design a digital logic circuit that will end up containing millions of transistors? In Appendix C we show that any digital logic circuit can be made from only three types of basic gates: AND, OR, and NOT. In fact, we will see that any digital logic circuit can be made using only NAND gates (or only NOR gates), where each NAND or NOR gate contains four transistors. These basic gates were provided in SSI chips using various technologies, the most popular being transistor-transistor logic (TTL). These TTL chips were the mainstay of digital design throughout the 1960s and 1970s. Many MSI TTL chips became available for performing all types of digital logic functions such as decoders, adders, multiplexers, comparators, and many others. By the 1980s thousands of gates could fit on a single chip. Thus, several different varieties of programmable logic devices (PLDs) were developed in which arrays containing large numbers of AND, OR, and NOT gates were arranged in a single chip without any predetermined function. Rather, the designer could design any type of digital circuit and implement it by connecting the internal gates in a particular way. This is usually done by opening up fuse links within the chip using computer-aided tools. Eventually the equivalent of many PLDs on a single chip led to complex programmable logic devices (CPLDs). Field Programmable Gate Arrays (FPGAs) A completely different architecture was introduced in the mid-1980’s that uses RAM-based lookup tables instead of AND-OR gates to implement combinational logic. These devices are called field programmable gate arrays (FPGAs). The device consists of an array of configurable logic blocks (CLBs) surrounded by an array of I/O blocks. The Spartan-3E from Xilinx also contains some blocks of RAM, 18 x 18 multipliers, as well as Digital Clock Manager (DCM) blocks. These DCMs are used to eliminate clock distribution delay and can also increase or decrease the frequency of the clock.

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