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DIGITAL DESIGN THROUGH VERILOG HDL

by Amity Kumar
Type: NoteInstitute: Amity University Specialization: Computer Science EngineeringDownloads: 31Views: 889Uploaded: 7 months agoAdd to Favourite

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DIGITAL DESIGN THROUGH VERILOG HDL by Amity Kumar

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Introduction to VHDL VHDL is an acronym for VHSlC Hardware Description Language (VHSIC is an acronym for Very High Speed Integrated Circuits). It is a hardware description language that can be used to model a digital system at many levels of abstraction ranging from the algorithmic level to the gate level. The complexity of the digital system being modeled could vary from that of a simple gate to a complete digital electronic system, or anything in between. The digital system can also be described hierarchically. Timing can also be explicitly modeled in the same description. VHDL resulted from work done in the ’70s and early ’80s by the U.S. Department of Defense. Its roots are in the ADA language, as will be seen by the overall structure of VHDL as well as other VHDL statements. VHDL usage has risen rapidly since its inception and is used by literally tens of thousands of engineers around the globe to create sophisticated electronic products. VHDL is a powerful language with numerous language constructs that are capable of describing very complex behavior. VHDL Terms VHDL is used to describe a model for a digital hardware device. This model specifies the external view of the device and one or more internal views. The internal view of the device specifies the functionality or structure, while the external view specifies the interface of the device through which it communicates with the other models in its environment _ Entity. All designs are expressed in terms of entities. An entity is the most basic building block in a design. The uppermost level of the design is the top-level entity. If the design is hierarchical, then the top-level description will have lower-level descriptions contained in it. These lower-level descriptions will be lower-level entities contained in the top-level entity description.  The entity describes the external interface to the model (specifies the inputs, outputs signals). It is the Hardware abstraction of a Digital system, but it does not provide any inner details.
_ Architecture. All entities that can be simulated have an architecture description. The architecture describes the behavior of the entity. A single entity can have multiple architectures. One architecture might be behavioral while another might be a structural description of the design. • The architecture describes the function/behavior of the model. Behavior of entity is defined by the relationship of the input to the output. It specifies the inner details of the circuit For examples relating to architecture & entity refer to presentation_1. _ Configuration. A configuration statement is used to bind a component instance to an entity-architecture pair. A configuration can be considered like a parts list for a design. It describes which behavior to use for each entity, much like a parts list describes which part to use for each part in the design. _ Package. A package is a collection of commonly used data types and subprograms used in a design. Think of a package as a toolbox that contains tools used to build designs. _ Driver. This is a source on a signal. If a signal is driven by two sources, then when both sources are active, the signal will have two drivers. _ Bus. The term “bus” usually brings to mind a group of signals or a particular method of communication used in the design of hardware. In VHDL, a bus is a special kind of signal that may have its drivers turned off. _ Attribute. An attribute is data that are attached to VHDL objects or predefined data about VHDL objects. Examples are the current drive capability of a buffer or the maximum operating temperature of the device.
_ Generic. A generic is VHDL’s term for a parameter that passes information to an entity. For instance, if an entity is a gate level model with a rise and a fall delay, values for the rise and fall delays could be passed into the entity with generics. _ Process. A process is the basic unit of execution in VHDL. All operations that are performed in a simulation of a VHDL description are broken into single or multiple processes. Architecture Body The internal details of an entity are specified by an architecture body using any of the following modeling styles: 1. As a set of interconnected components (to represent structure), 2. As a set of concurrent assignment statements (to represent dataflow), 3. As a set of sequential assignment statements (to represent behavior), 4. Any combination of the above three. Structural Style of Modeling In the structural style of modeling, an entity is described as a set of interconnected components. Dataflow Style of Modeling In this modeling style, the flow of data through the entity is expressed primarily using concurrent signal assignment statements. The structure of the entity is not explicitly specified in this modeling style, but it can be implicitly deduced. Behavioral Style of Modeling In contrast to the styles of modeling described earlier, the behavioral style of modeling specifies the behavior of an entity as a set of statements that are executed sequentially in the specified order. This set of sequential statements, that are specified inside a process statement, do not explicitly specify the structure of the entity but merely specifies its functionality. A process statement is a concurrent statement that can appear within an architecture body. Mixed Style of Modeling It is possible to mix the three modeling styles that we have seen so far in a single architecture body. That is, within an architecture body, we could use component
instantiation statements (that represent structure), concurrent signal assignment statements (that represent dataflow), and process statements (that represent behavior). Basic Language Elements Identifiers An identifier in VHDL is composed of a sequence of one or more characters. A legal character is an upper-case letter (A... Z), or a lower-case letter (a. .. z), or a digit (0 . . . 9) or the underscore ( _ ) character. The first character in an identifier must be a letter and the last character may not be an underscore. Lower-case and upper-case letters are considered to be identical when used in an identifier; as an example. Count, COUNT, and CouNT, all refer to the same identifier. Also,-two underscore characters cannot appear consecutively. Some more examples of identifiers are DRIVE_BUS SelectSignal RAM_Address SET_CK_HIGH CONST32_59 r2d2 Comments in a description must be preceded by two consecutive hyphens (-); the comment extends to the end of the line. Comments can appear anywhere within a description. Examples are --This is a comment; it ends at the end of this line. --To continue a comment onto a second line, separate 2 hyphens The language defines a set of reserved words; such as integer, real, etc.These words, also called keywords, have a specific meaning in the language, and therefore, cannot be used as identifiers. Data Objects A data object holds a value of a specified type. It is created by means of an object declaration. An example is variable COUNT: INTEGER; This results in the creation of a data object called COUNT which can hold integer values. The object COUNT is also declared to be of variable class.

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