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VLSI Design

by Ravi Kumar Mishra
Type: NoteInstitute: VTU Specialization: Electronics and Communication EngineeringDownloads: 72Views: 1696Uploaded: 5 months agoAdd to Favourite

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Ravi Kumar Mishra
Ravi Kumar Mishra
Sub: Fundamentals of CMOS VLSI Sub code: 10EC56 Fundamentals of CMOS VLSI Sub code: 10EC56 No. of lecture Hrs/Week: 04 Total Hours:52 IA Marks:25 Exam Hours:03 Exam Marks: 100 PART-A Unit 1: Basic MOS Technology Integrated circuits era, enhancement and depletion mode MOS transistors. nMOS fabrication. CMOS fabrication, Thermal aspects of processing, BiCMOS technology, production of E-beam masks. 3 Hours MOS transistor theory Introduction, MOS device design equations, the complementary CMOS inverter-DC characteristics, static load MOS inverters, the differential inverter, the transmission gate, tristate inverter. 4 Hours Unit-2: Circuit Design Processes MOS layers, stick diagrams, Design rules and layout- lambda-based design and other rules. Examples, layout diagrams, symbolic diagram, tutorial exercises. Basic physical design of simple logic gates. 4 Hours 3 Hours Unit 3: CMOS Logic Structures CMOS complementary logic, BiCMOS logic, Pseudo-nMOS logic, Dynamic CMOS logic, clocked CMOS logic, Pass transistor logic, CMOS domino logic cascaded voltage switch logic (CVSL). 6 Hours Unit-4: Basic circuit concepts Sheet resistance, area capacitances, capacitances calculations. The delay unit, inverter delays, driving capacitive loads, propagation delays, wiring capacitances . 3 Hours Dept of ECE,SJBIT
Sub: Fundamentals of CMOS VLSI Sub code: 10EC56 Scaling of MOS circuits Scaling models and factors, limits on scaling, limits due to current density and noise. 3 Hours PART-B Unit-5: CMOS subsystem design Architectural issues, switch logic, gate logic, design examples-combinational logic, clocked circuits. Other system considerations. 3 Hours Clocking strategies 2 Hours Unit-6: CMOS subsystem design processes General considerations, process illustration, ALU subsystem, adders, multipliers. 6 Hours Unit-7: Memory registers and clock Timing considerations, memory elements, memory cell arrays. 6 Hours Unit-8: Testability Performance parameters, layout issues I/O pads, real estate, system delays, ground rules for design, test and testability. 7 Hours TEXT BOOKS 1. Douglas A. Pucknell & Kamran Eshraghian, “Basic VLSI Design” PHI 3rd Edition (original Edition – 1994), 2005. 2. Neil H. E. Weste and K. Eshragian,” Principles of CMOS VLSI Design: A System Perspective,” 2nd edition, Pearson Education (Asia) Pvt. Ltd., 2000. History of VLSI Dept of ECE,SJBIT
Sub: Fundamentals of CMOS VLSI Sub code: 10EC56 3. CMOS VLSI DESIGN—A circuits and systems perpective. 3rd edition N.H.Weste and David Harris. Addison-wesley. REFERENCE BOOKS 1. R.Jacob Baker.CMOS circuit design, layout and simulation. 2. Fundamentals of semiconductor devices: M.K.Achuthan and K.N.Bhat. 3. CMOS digital Integrated circuits: Analysis and design: Sung-Mo Kang and Yusuf Leblebici. 4. Analysis and design of digital integrated circuits: D.A.Hodges, Jackson and Saleh. Dept of ECE,SJBIT
Sub: Fundamentals of CMOS VLSI Sub code: 10EC56 INDEX SHEET TOPIC SL.NO 1 UNIT 1: Basic MOS technology: PAGE NO. 1-38 Integrated circuits era, Enhancement and depletion mode 1-9 MOS transistors 7-9 nMOS fabrication CMOS fabrication 9-19 Thermal aspects of processing, BiCMOS technology, 19-21 Production of E-beam masks MOS Transistor Theory: 2 Introduction, MOS Device Design Equations, 22-25 The Complementary CMOS Inverter – DC Characteristics, 25-31 The Differential Inverter, 31-34 Static Load MOS Inverters, 33-34 The Transmission Gate 35-36 Tristate Inverter 37-38 UNIT 2: CIRCUIT DESIGN PROCESSES 39-60 MOS layers. Stick diagrams. 39-44 Design rules and layout 45-48 Lambda-based design and other rules. 48-49 Examples. Layout diagrams. 49-50 Symbolic diagrams 49-50 Tutorial exercises, Basic Physical Design of Simple logic gates 51-60 Dept of ECE,SJBIT

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