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Note for Computer Organisation and Architecture - COA by Siddharth Rajput

  • Computer Organisation and Architecture - COA
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UNIT II: COMPUTER ORGANIZATION AND ARCHITECTURE LAST SIX YEARS' GATE ANALYSIS 7 Number of questions 6 5 Marks 1 Marks 2 Total number of questions 4 3 2 1 0 2015 2014 2013 2012 2011 2010 Concepts on which questions were asked in the previous six years Chapter 2.indd 55 Year Concepts 2015 Cache memory, Memory, Pipelining, Main memory, Pipeline, Anti-dependency, Instruction format, Byte Addressable memory, Pipeline, Three-address code 2014 Memory access, pipelining 2013 Cache memory, hard disk, pipelining, registers, micro-operations 2012 Pipelining, ROM, cache, file system 2011 Cache memory, interrupts 2010 Memory, pipelining, registers, cache memory 4/9/2015 9:49:42 AM

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Chapter 2.indd 56 4/9/2015 9:49:42 AM

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CHAPTER 2 COMPUTER ORGANIZATION AND ARCHITECTURE Syllabus: Machine instructions and addressing modes, ALU and data path, CPU control design, memory interface, I/O interface (interrupt and DMA mode), instruction pipelining, cache and main memory, secondary storage 2.1  INTRODUCTION 2.2  COMPUTER ARCHITECTURE Computer architecture and organization is the science of interconnecting hardware components, designing and configuring the hardware/software interface to fulfill functional and performance goals of a computer. This chapter outlines the basic hardware structure of a modern digital programmable computer, the basic laws for performance evaluation, designing the control and data path hardware for a processor, concept of pipelining for executing machine instructions simultaneously and designing fast memory and storage systems. 2.2.1  Register Set The computer needs registers for processing and manipulating data and for holding memory addresses that are available to the machine-code programmer. Some registers for a basic computer are given in Table 2.1. Table 2.1 |   Types of registers and their functions Register Symbol Register Name Function Computer architecture deals with the structure and behaviour of computer system as viewed by the user. It encompasses instruction formats, the instruction set architecture (ISA) and addressing modes. DR Data register Holds memory operand ACC Accumulator Special purpose processor register Computer organization deals with the operation and interconnection of the various hardware components. AR Address register Holds address for memory (Continued) Chapter 2.indd 57 4/9/2015 9:49:42 AM

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58     Chapter 2:  Computer Organization and Architecture  Table 2.1 |   Continued When the system consists of multiple frequent cases, where i is the number of frequent cases: Register Register Symbol Name Function IR Holds an instruction that is to be executed Holds address of instruction to be executed next Holds temporary data if required Holds input character Holds output character ( Instruction register Program counter PC TR Temporary register Input register Output register INPR OUTR Amdahl’s law focused on performance gain after enhancing the system. The performance gain is denoted by Soverall and ET stands for execution time. Performance of the system with enhancement Performance of the system without enhancement Soverall = 1 ETnew  1 ETold Soverall = (2.1) ETold ETnew After enhancement, the system consists of two portions: unenhanced and enhanced portion. To calculate ETnew, the following two factors are needed:   1.  Fractionenhance (F): It indicates how much portion of the old system undergoes enhancement.   2.  Speedenhance (S): It indicates how many times the new portion is running faster than the old portion. 1 ETnew F Performancenew F ETold F = = 1 ETold F Performanceold F ETnew F ETold F S On the basis of the above factor, So, Solution: Here S = 2, F = 0.1 −1 = 1.052 2.3  MACHINE INSTRUCTIONS AND ADDRESSING MODES Machine instruction is an individual machine code. The complete set of all machine codes recognized by a particular processor makes its Instruction Set. Instructions can be grouped according to the function they perform. The number of ways by which arguments for these machine instructions can be specified constitutes the addressing modes for a processor. 2.3.1  Machine Instructions An instruction is a command to the microprocessor to perform a given task. Most computer instructions are classified as follows: ETnew = ET of the unenhanced portion + ET of enhanced portion S= −1 Problem 2.1: Consider a hypothetical processor used in mathematical model simulation. It consists of two functional units, floating point and integer. The floating point is enhanced then it runs two times faster, but only 10% of the instructions are floating point. What is the speed up? 0.1   Soverall = (1 − 0.1) + 2   2.2.2  Quantitative Principles to Design High-Performance Processor Soverall = ) Fi   Soverall =  1 − ∑ Fi + ∑  S  ETnew F =   1.  Data transfer instructions: These instructions move data from one place to another in the computer without changing the data content. Example: LOAD, MOVE, IN, OUT, PUSH, STORE.   2. Data manipulation instructions: These instructions perform arithmetic, logical and shift operations on data. Example: ADD, SUB, MUL, DIV, INC, AND, XOR, OR, SHR, SHL, ROR, ROL.   3. Program control instructions: These instructions may change the address value in program counter and cause the normal sequential flow to change. ETold F S On the basis of the number of address fields in an instruction, they are classified as follows: Substitute the value of ET in Eq. (2.1): ETold F ETnew F = ETold (1 − F ) + S Let ETold = 1,   1.  Three-address instruction: Computer with three-address instruction format can use each address field to specify two sources and a destination, which can be either a processor register or a memory operand. It results in short program but requires too many bits to specify three addresses. ETnew F = ETold (1 − F ) + Soverall = Chapter 2.indd 58 1 F  = (1 − F ) +  (1 − F ) + (F S )  S −1 Example: ADD R1, A, B (R1 ← M[A] + M[B]) 4/9/2015 9:49:45 AM

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