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By Mr. Njubo Nelson (0782785766) Saturday, September 29, 2018 CEN4101 Handout 1/2 Microprocessors and Microcontroller Systems CEN4101 Microprocessor - Introduction Definition Microprocessor is a controlling unit of a micro-computer, fabricated on a small chip capable of performing ALU (Arithmetic Logical Unit) operations and communicating with the other devices connected to it. Overview: Microprocessor consists of an ALU, register array, and a control unit. ALU performs arithmetical and logical operations on the data received from the memory or an input device. Register array consists of registers identified by letters like B, C, D, E, H, L and accumulator. The control unit controls the flow of data and instructions within the computer. Figure: Block Diagram of a Basic Microcomputer How does a Microprocessor Work? The microprocessor follows a sequence: Fetch, Decode, and then Execute. Initially, the instructions are stored in the memory in a sequential order. The microprocessor fetches those instructions from the memory, then decodes them and executes those instructions till STOP instruction is reached. Later, it sends the result in binary to the output port. Between these processes, the register stores the temporarily data and ALU performs the computing functions. List of Terms Used in a Microprocessor Here is a list of some of the frequently used terms in a microprocessor environments− • Instruction Set − It is the set of instructions that the microprocessor can understand. • Bandwidth − It is the number of bits processed in a single instruction. • Clock Speed − It determines the number of operations per second the processor can perform. It is expressed in megahertz (MHz) or gigahertz (GHz).It is also known as Clock Rate. • Word Length − It depends upon the width of internal data bus, registers, ALU, etc. An 8-bit microprocessor can process 8-bit data at a time. The word length ranges from 4 bits to 64 bits depending upon the type of the microcomputer. • Data Types − The microprocessor has multiple data type formats like binary, BCD, ASCII, signed and unsigned numbers. Features of a Microprocessor Here is a list of some of the most prominent features of any microprocessor − • Cost-effective − The microprocessor chips are available at low prices and results its low cost. • Size − The microprocessor is of small size chip, hence is portable. • Low Power Consumption − Microprocessors are manufactured by using metaloxide semiconductor technology, which has low power consumption. KIU Page 1 of 29 SEAS

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By Mr. Njubo Nelson (0782785766) Saturday, September 29, 2018 CEN4101 Handout 1/2 Versatility − The microprocessors are versatile because the same chip can be used in a number of applications by configuring the software program. • Reliability − The failure rate of an IC in microprocessors is very low, hence it is reliable. • Microprocessor – Architecture: (1) CISC & RISC Architecture Architecture of Central Processing Unit drives its working ability from the instruction set architecture upon which it is designed. Instruction Set Architecture can be defined as an interface to allow easy communication between the programmer and the hardware. ISA prepares microprocessor to respond to all the user commands like execution of data, copying data, deleting it, editing it and other diverse operations. Some major terms that are often used in ISA are: Instruction Set: It is a group of instructions that can be given to the computer. These instructions direct the computer in terms of data manipulation. A typical instruction consists of two parts: Opcode and Operand. Opcode or operational code is the instruction applied. It can be loading data, storing data etc. Operand is the memory register or data upon which instruction is applied. Addressing Modes: Addressing modes are the manner in the data is accessed. Depending upon the type of instruction applied, addressing modes are of various types such as direct mode where straight data is accessed or indirect mode where the location of the data is accessed. Processors having identical ISA may be very different in organization. Processors with identical ISA and nearly identical organization are still not nearly identical. CPU performance is given by the fundamental law: Thus, CPU performance is dependent upon Instruction Count, CPI (Cycles per instruction) and Clock cycle time. And all three are affected by the instruction set architecture. Program Compiler Instruction Set Architecture Microarchitecture Physical Design Instruction Count x x x CPI x x x Clock x x x This underlines the importance of the instruction set architecture. There are two prevalent instruction set architectures: (a) Complex Instruction Set Architecture (CISC): The CISC approach attempts to minimize the number of instructions per program, sacrificing the number of cycles per instruction. (b) Reduced Instruction Set Architecture (RISC): RISC does the opposite, reducing the cycles per instruction at the cost of the number of instructions per program Subsequent sections will discuss RISC, CISC designs and their characteristics. CISC Architecture CISC processors were designed to simplify compilers and to improve performance under constraints such as small and slow memories. The emphasis is on building complex instructions directly into the hardware. CISC is intended to ease compiler writing, improve execution efficiency, and to support more complex high level languages. It shifts most of the burden of generating machine instructions to the processor. For KIU Page 2 of 29 SEAS

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By Mr. Njubo Nelson (0782785766) Saturday, September 29, 2018 CEN4101 Handout 1/2 example, instead of having to make a compiler write long machine instructions to calculate a square-root, a CISC processor would have a built-in ability to do this. Cache – Is a hardware or software that stores data so that future requests for that data can be served faster. TYPICAL CHARACTERISTICS OF CISC ARCHITECTURE Most CISC hardware architectures have several characteristics in common: a) Complex instruction-decoding logic, it is driven by the need for a single instruction to support multiple addressing modes. b) Small number of general purpose registers. Instructions which operate directly on memory, and only the limited amount of chip space is dedicated for general purpose registers. c) Several special purpose registers. Many CISC designs set aside special registers for the stack pointer, interrupt handling, and so on. This can simplify the hardware design somewhat, at the expense of making the instruction set more complex. d) 'Condition code" register. This register reflects whether the result of the last operation is less than, equal to, or greater than zero and records if certain error conditions occur. e) Several cycles may be required to execute one instruction. CISC PROCESSORS –EXAMPLES 1. IBM 370/168; Introduced in 1970, this CISC design is a 32 bit processor with 4 general purpose and 4 64-bit floating point registers. 2. VAX 11/780; This CISC design is again a 32-bit processor from DEC (Digital Equipment Corporation). It supports large number of addressing modes and machine instructions 3. Intel 80486; Launched in 1989, this CISC processor has instructions with their lengths varying from 1 to 11 and had 235 instructions. RISC Architecture RISC, or Reduced Instruction Set Computer is a type of microprocessor architecture that utilizes a small, highly-optimized set of instructions, rather than a more specialized set of instructions often found in other types of architectures. It is designed to reduce the execution time by simplifying the instruction set of the computer. Using RISC processors, each instruction requires only one clock cycle to execute results in uniform execution time. This reduces the efficiency as there are more lines of code; hence more RAM is needed to store the instructions. The compiler also has to work more to convert high-level language instructions into machine code. KIU Page 3 of 29 SEAS

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By Mr. Njubo Nelson (0782785766) Saturday, September 29, 2018 CEN4101 Handout 1/2 Certain design features have been characteristics of most RISC processors. a) One Cycle Execution Time: RISC processors have a CPI (clock per instruction) of one cycle. b) Pipelining: A technique that allows simultaneous execution of parts, or stages, of instructions to more efficiently process instructions. c) Large Number of Registers. The RISC design philosophy generally incorporates a larger number of registers to prevent large amounts of interactions with memory Typical Characteristics of RISC Architecture 1. Simple Instructions. The designers of CISC architectures anticipated extensive use of complex instructions. However, in practice, it turns out that compilers mostly ignore these instructions; the fact has been demonstrated by several empirical studies. Because of these reasons, RISC architectures use simpler instructions. Limited fixed length instructions (typically 4 bytes) are provided. No instructions combine load/store with arithmetic. 2. Few Data types: CISC ISA support a variety of data structures, from simple data types such as integers and characters to complex data structures such as records and structures. Empirical data suggest that complex data structures are used relatively infrequently. RISC supports a few simple data types efficiently and the complex/missing data types are synthesized from them. 3. Simple Addressing Modes: CISC designs provide a large number of addressing modes to support complex data structures as well as to provide flexibility to access operands. However it leads to problems of variable instruction execution times & variable-length instructions. This causes inefficient instruction decoding and scheduling. RISC designs use simple addressing modes and fixed length instructions to facilitate pipelining. Memory-indirect addressing is not provided. 4. Identical General Purpose Registers. RISC designs allow any register to be used in any context, simplifying compiler designs. 5. Harvard Architecture: RISC designs often use a Harvard memory model, where the instruction stream and the data stream are conceptually separated Pipelining-Unique Feature of RISC: Typically, after the execution of one instruction is over, execution of next instruction starts. But, processors which support pipelining, the instruction execution time is divided in several stages (machine cycles). As KIU Page 4 of 29 SEAS

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