Note for Computer Organization - CO by Akash Sharma

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Computer Organisation - ( 1 - 1 )
Memory Organisation - ( 2 - 2 )
Memory Configuration - ( 3 - 3 )
Byte address V/S Word address - ( 4 - 7 )
Time multiplexed pins - ( 8 - 8 )
Memory Interfacing - ( 9 - 9 )
Communication Channel - ( 10 - 13 )
Bus Configurations - ( 14 - 16 )
Fetch Cycle - ( 17 - 19 )
Execution Cycle - ( 20 - 28 )
Register to Register ref Architecture - ( 29 - 32 )
Execution Cycle - ( 33 - 33 )
PSW/Flag Register - ( 34 - 38 )
Control Flags - ( 39 - 39 )
Addressing Modes - ( 40 - 48 )
Transfer of Control flow AM - ( 49 - 55 )
Types of Operations - ( 56 - 58 )
Data Manipulation - ( 59 - 60 )
Interrupts - ( 61 - 65 )
Register Organisation in RISC processor - ( 66 - 66 )
Components of the Computer - ( 67 - 70 )
Control Unit - ( 71 - 72 )
Microprogrammed Control unit - ( 73 - 76 )
CPU time calculation - ( 77 - 80 )
Pipelining - ( 81 - 84 )
Types of pipelins - ( 85 - 90 )
Advanced Pipeline - ( 91 - 100 )
Scheduling - ( 101 - 104 )
Memory Organisation - ( 105 - 108 )
Cache Memory - ( 109 - 112 )
Mapping Techniques - ( 113 - 119 )
Set associative Mapping - ( 120 - 134 )
Multilevel Caches - ( 135 - 139 )
Input Output Organisation - ( 140 - 141 )
Direct Memory Access - ( 142 - 142 )

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