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Advanced Computer Architecture

by Akash SharmaAkash Sharma
Type: NoteCourse: B.Tech Specialization: Information Technology EngineeringOffline Downloads: 39Views: 304Uploaded: 15 days ago

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Advanced Computer Architecture by Akash Sharma

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Akash Sharma
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Akash Sharma
Akash Sharma
EC6009 ADVANCED COMPUTER ARCHITECTURE ww UNIT I LTPC 3 0 03 w.L FUNDAMENTALS OF COMPUTER DESIGN 9 Review of Fundamentals of CPU, Memory and IO – Trends in technology, power, ect energy and cost, Dependability - Performance Evaluation UNIT II ure INSTRUCTION LEVEL PARALLELISM no 9 ILP concepts – Pipelining overview - Compiler Techniques for Exposing ILP – tes Dynamic Branch Prediction – Dynamic Scheduling – Multiple instruction Issue – Hardware Based Speculation – Static scheduling - Multi-threading - Limitations of ILP – Case Studies. UNIT III DATA-LEVEL PARALLELISM .in 9 Vector architecture – SIMD extensions – Graphics Processing units – Loop level parallelism. UNIT IV THREAD LEVEL PARALLELISM 9 Symmetric and Distributed Shared Memory Architectures – Performance Issues – Synchronization – Models of Memory Consistency – Case studies: Intel i7 Processor, SMT & CMP Processors. UNIT V MEMORY AND I/O 9 Cache Performance – Reducing Cache Miss Penalty and Miss Rate – Reducing Hit Time – Main Memory and Performance – Memory Technology. Types of Storage Devices – Buses – RAID – Reliability, Availability and Dependability – I/O Performance Measures. TOTAL: 45 PERIODS TEXT BOOK: 1. John L Hennessey and David A Patterson, “Computer Architecture A Quantitative Approach”, Morgan Kaufmann/ Elsevier, Fifth Edition, 2012. REFERENCES: 1. Kai Hwang and Faye Briggs, “Computer Architecture and Parallel Processing”, Mc Graw-Hill International Edition, 2000. 2. Sima D, Fountain T and Kacsuk P, ”Advanced Computer Architectures: A Design Space Approach”, Addison Wesley, 2000. 2
EC 6009 ww ADVANCED COMPUTER ARCHITECTURE 3003 1. Aim and Objective of the subject w.L  Understand the micro-architectural design of processors  Learn about the various techniques used to obtain performance ect improvement and power savings in current processors  ure To familiarize the students with Instruction Level Parallelism and Data-Level Parallelism no tes  To expose the students to the concept of Thread Level Parallelism  To familiarize the students with Memory and I/O .in 2. Need and Importance for the study of the subject  Evaluate performance of different processor architectures with respect to various parameters  Analyze performance of different Instruction Level Parallelism techniques  Evaluate performance of Data-Level Parallelism andThread Level Parallelism  Identify cache and memory related issues in multi-processors 3. Industry Connectivity and Latest Developments  Latest processor’s architecture in computers (SMT, CMP, Intel i7 Processor’s) are analyzed.  VLIW and Vector architectures play a vital role in industries 4. Industry Visit (Planned if any) --NIL--- 3
SCAD GROUP OF INSTITUTIONS DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING Detailed Lesson Plan Name of the Subject & Code : EC6009 Advanced Computer Architecture Name of the Faculty: 1. Mr.R.Kabilan, AP/ECE, FXEC 2. Mr.G. Jayaraman, AP/ECE, FXEC 3. Mr.B.Pradheep T Rajan, AP/ECE, FXEC ww TEXT BOOK: w.E 1. John L Hennessey and David A Patterson, “Computer Architecture A Quantitative Approach”, Morgan Kaufmann/ Elsevier, Fifth Edition, 2012. REFERENCES: asy 1. Kai Hwang and Faye Briggs, “Computer Architecture and Parallel Processing”, En Mc Graw-Hill International Edition, 2000. gin 2. Sima D, Fountain T and Kacsuk P, ”Advanced Computer Architectures: A Design Space Approach”, Addison Wesley, 2000. 4 eer ing .ne t
Downloaded From : www.Lecturenotes.in Si. Unit No 1 I 2 3 4 5 6 I I I I I 7 8 9 10 11 II II II II II 12 II 13 II 14 II 15 II 16 17 18 19 III III III III 20 IV 21 IV 22 IV 23 IV 24 IV 25 IV 26 V 27 28 29 30 V V V V 31 V 32 V Hours Cumulative Books required / Hrs Referred planned UNITI FUNDAMENTALS OF COMPUTER DESIGN Review of Fundamentals of CPU, 3 3 T1 Memory, IO Trends in technology Instructions 1 4 T1 Power, Energy 2 6 T1 Cost 1 7 T1 Dependability 1 8 T1 Performance Evaluation 1 9 T1 UNITII INSTRUCTION LEVEL PARALLELISM ILP concepts, Pipelining overview 1 10 T1 Compiler Techniques for Exposing ILP 2 12 T1 Dynamic Branch Prediction 1 13 T1 Dynamic Scheduling 1 14 T1 Hardware Based Speculation 1 15 T1 Multiple instruction Issue - Static 1 16 T1 scheduling Multi-threading 1 17 T1 Limitations of ILP 1 18 T1 Case Studies 1 19 T1 UNIT III DATA-LEVEL PARAL1LELISM Vector architecture 2 21 T1 SIMD extensions 3 24 T1 Graphics Processing units 2 26 T1 Loop level parallelism 2 28 T1 UNITIV THREAD LEVEL PARALLELISM Symmetric Shared Memory 2 30 T1 Architectures Distributed Shared Memory 2 32 T1 Architectures Performance Issues 1 33 T1 Synchronization 1 34 T1 Models of Memory Consistency 1 35 T1 Case studies: Intel i7 Processor, SMT 2 37 T1 Processor, CMP Processor UNITV MEMORY ANDI/O Cache Performance- Reducing Cache Miss Penalty, Miss Rate, Reducing Hit 3 40 T1 Time Main Memory and Performance 1 41 T1 Memory Technology 1 42 T1 Types of Storage Devices 1 43 T1 Buses 1 44 T1 RAID – Reliability, Availability and 1 45 T1 Dependability I/O Performance Measures 1 46 T1 Topics to be covered Page No. 2-17 17-21 21-26 27-33 33-36 36-44 148-156 156-162 162-167 167-183 183-192 192-202 223-232 213-221 247-254 264-282 282-288 288-315 315-322 366-378 378-386 395-400 386-391 392-395 401-405 78-96 72-78 96-105 D12-35 I16 D44-59 D15-16 Total: 46 Hours 5 Downloaded From : www.Lecturenotes.in

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