Note for Verilog HDL - VH By Veena I Puranikmath
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S. S. EDUCATION TRUST (R) S. G. BALEKUNDRI INSTITUTE OF TECHNOLOGY VERILOG HDL [15EC53] Notes as per VTU CBCS Syllabus for V Semester Electronics & Communication Engineering Ms. Veena I Puranikmath BE., M.Tech (Digital Communication and Networking) Assistant Professor Department of Electronics & Communication Engineering S G Balekundri Institute of Technology, Shivabasav Nagar, Belagavi-590010. Karnataka State. Email: Veenaip043@gmail.com Mobile: 8867129509
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Verilog HDL SEMESTER – V (E&CE) Subject Code Number of Lecture Hours/Week Total Number of Lecture Hours Course objectives: 15EC53 04 50 IA Marks Exam Hours Exam Marks 20 03 80 This course will enable students to: Differentiate between Verilog and VHDL descriptions. Learn different Verilog HDL and VHDL constructs. Familiarize the different levels of abstraction in Verilog. Understand Verilog Tasks and Directives. Understand timing and delay Simulation. Learn VHDL at design levels of data flow, behavioral and structural for effective modeling of digital circuits. CHAPTERS Teaching Hours (RBT)Level 10 Hours L1, L2, L3 10 Hours L1, L2, L3 10 Hours L1, L2, L3 10 Hours L1, L2, L3 10 Hours L1, L2, L3 MODULE 1 OVERVIEW OF DIGITAL DESIGN WITH VERILOG HDL: Evolution of CAD, emergence of HDLs, typical HDL-flow, why Verilog HDL?, trends in HDLs. HIERARCHICAL MODELING CONCEPTS: Top-down and bottom-up design methodology, differences between modules and module instances, parts of a simulation, design block, stimulus block. MODULE 2 BASIC CONCEPTS: Lexical conventions, data types, system tasks, compiler directives. MODULES AND PORTS: Module definition, port declaration, connecting ports, hierarchical name referencing. MODULE 3 GATE-LEVEL MODELING MODELING: using basic Verilog gate primitives, description of and/or and buf/not type gates, rise, fall and turn-off delays, min, max, and typical delays. DATAFLOW MODELING: Continuous assignments, delay specification, expressions, operators, operands, operator types. MODULE 4 BEHAVIORAL MODELING: Structured procedures, initial and always, blocking and non-blocking statements, delay control, generate statement, event control, conditional statements, Multiway branching, loops, sequential and parallel blocks. MODULE 5 INTRODUCTION TO VHDL INTRODUCTION: Why use VHDL?, Shortcomings, Using VHDL for Design Synthesis, Design tool flow, Font conventions. ENTITIES AND ARCHITECTURES: Introduction, A simple design, Design entities, Identifiers, Data objects, Data types, and Attributes.
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Course Outcomes: At the end of the course, students will be able to: Write Verilog programs in gate, dataflow (RTL), behavioral and switch modeling levels of Abstraction. Write simple programs in VHDL in different styles. Design and verify the functionality of digital circuit/system using test benches. Identify the suitable Abstraction level for a particular digital design. Write the programs more effectively using Verilog tasks and directives. Perform timing and delay Simulation. Question paper pattern: The question paper will have ten questions Each full question consists of 16 marks. There will be 2 full questions (with a maximum of three sub questions) from each module. Each full question will have sub questions covering all the topics under a module The students will have to answer 5 full questions, selecting one full question from each module Graduating Attributes (as per NBA) Engineering Knowledge Problem Analysis Design / development of solutions (partly) Text Book: 1. Samir Palnitkar, “Verilog HDL: A Guide to Digital Design and Synthesis”, Pearson Education, Second Edition. 2. Kevin Skahill, “VHDL for Programmable Logic”, PHI/Pearson education, 2006. Reference Books: 1. Donald E. Thomas, Philip R. Moorby, “The Verilog Hardware Description Language”, Springer Science+Business Media, LLC, Fifth edition. 2. Michael D. Ciletti, “Advanced Digital Design with the Verilog HDL” Pearson (Prentice Hall), Second edition. 3. Padmanabhan, Tripura Sundari, “Design through Verilog HDL”, Wiley, 2016 or earlier.
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INDEX SL.NO 1 MODULES CONTENTS MODULE 1 OVERVIEW OF DIGITAL DESIGN WITH VERILOG HDL: Evolution of CAD Emergence of HDLs Typical HDL-flow Why Verilog HDL Trends in HDLs HIERARCHICAL MODELING CONCEPTS: Top-down and bottom-up design methodology Differences between modules and module instances Parts of a simulation Design block Stimulus block. PAGE NO. 1-22 1 1 6 4 9 11 15 19 21 22 25-58 2 MODULE 2 BASIC CONCEPTS: Lexical conventions 25 Data types System tasks 30 41 Compiler directives. MODULES AND PORTS: Module definition Port declaration Connecting ports Hierarchical name referencing. 45 47 51 56 58 58-87 3 MODULE 3 GATE-LEVEL MODELING MODELING: Using basic Verilog gate primitives Description of and/or and buf/not type gates Rise, fall and turn-off delays Min, Max, Typical delays. DATAFLOW MODELING: Continuous assignments Delay specification Expressions Operators Operands Operator types 61 61 74 75 81 83 86 86 86 87 111-131 4 MODULE 4 BEHAVIORAL MODELING: Structured procedures initial and always Blocking and Non-Blocking Statements Delay control Event control Conditional statements Multi way branching loops. 111 111 115 121 125 129 131
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