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**NBN sinhgad college of engineering -**- Electronics and Communication Engineering
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Subject: Electronics Technology (SE Mechanical) Prof. S.T. Waware UNIT-5 Digital Circuits 5.1 Definations: Combinational Circuits: The circuits whose output value depends on the present input at that instant called as “Combinational Circuits”. That means Output= f (present input) The combinational circuit don’t have any memory. Examples: All Gates, Multiplexers, Decoders etc. Fig.5.1. Combinational circuits Sequential Circuits: The circuits whose outputs dependent upon present input and past inputs/output of the circuit called as “Sequential logic Circuits”. That means Output= f (present input + Past input/output ) The sequential circuit have memory to store the past output (history). Examples: Flip flops, Registers, counters etc. Fig. 5.2. Sequential logic Circuit. N B Navale College of Engineering, Solapur 1

Subject: Electronics Technology (SE Mechanical) Prof. S.T. Waware Note: Remember the Truth Table of NAND Gates and NOR Gates Truth Table of NAND Gate Truth Table of NOR Gate Inputs Outputs Inputs Outputs A 0 0 1 1 B 0 1 0 1 Y= A.B 1 1 1 0 A B Y= A+B 0 0 1 0 1 0 1 0 0 1 1 0 __________________________________________________________________ 5.2 Flip Flops: 1. The basic 1-bit digital memory circuit is known as a flip-flop. It can have only two states, either the 1 state or the 0 state. A flip-flop is also known as a bistable multivibrator. 2. Flip-flops can be obtained by using NAND or NOR gates. The general block diagram representation of a flip-flop is shown in Figure 5.3. It has one or more inputs and two outputs. Fig.5.3 Block Diagram of Flip Flop 3. The two outputs are complementary to each other. If Q is 1 i.e., Set, then Q' is 0; if Q is 0 i.e., Reset, then Q' is 1. That means Q and Q' cannot be at the same state simultaneously. 4. If it happens by any chance, it violates the definition of a flip-flop and hence is called an undefined or inhibited condition. 5. Normally, the state of Q is called the state of the flip-flop, whereas the state of Q' is called the complementary state of the flip-flop. N B Navale College of Engineering, Solapur 2

Subject: Electronics Technology (SE Mechanical) Prof. S.T. Waware 5.3 Latch: Fig5.3 Basic Latch As shown in fig. 5.3, consists of two inverters G1 and G2 (NAND gates are used as inverters). The output of G1 is connected to the input of G2 (A2) and the output of G2 is connected to the input of G1 (A1). Let us assume the output of G1 to be Q = 0, which is also the input of G2 (A2 = 0). Therefore, the output of G2 will be Q' = 1, which makes A1 = 1 and consequently Q = 0 which is according to our assumption. Similarly, we can demonstrate that if Q = 1, then Q' = 0 and this is also consistent with the circuit connections. Hence we see that Q and Q' are always complementary. And if the circuit is in 1 state, it continues to remain in this state and vice versa is also true. Since this information is locked or latched in this circuit, therefore, this circuit is also referred to as a latch. In this circuit there is no way to enter the desired digital information to be stored in it. 5.4. Types of Flip Flops: The flip flop is memory cell which can stored the one bit of information at a time. The Flip-Flops are classified into four types as, 1. Set- Reset Flip-Flop (S-R Flip-Flop) 2. Delay Flip-Flop (D Flip-Flop) 3. J-K Flip-Flop 4. Toggle Flip-Flop (T Flip-Flop). N B Navale College of Engineering, Solapur 3

Subject: Electronics Technology (SE Mechanical) Prof. S.T. Waware 5.4.1. Set- Reset Flip-Flop (S-R Flip-Flop) Using NAND Gates : Que: Explain S-R Flip-Flop using NAND gate in detail. Fig.5.4(a). Clocked S-R Flip-Flop (5 Marks) Fig.5.4(b). Symbol of SR F/F As shown in above figure 5.4 the clocked S-R flip-Flop with logical symbol is shown. The working of S-R flip-flop is divided into four cases Case 1. If S = R = 0, and the clock pulse is not applied, the output of the flip-flop remains in the present state (Qn). Even if S = R = 0, and the clock pulse is applied, the output at the end of the clock pulse is the same as the output before the clock pulse, i.e., Qn+1 =Qn. Case 2. For S = 0 and R= 1, if the clock pulse is applied (i.e.,CLK = 1), the output of NAND gate 1 becomes 1; whereas the output of NAND gate 2 will be 0. Now a 0 at the input of NAND gate 4 forces the output to be 1, i.e., Q' = 1.This 1 goes to the input of NAND gate 3 to make both the inputs of NAND gate 3 as 1, which forces the output of NAND gate 3 to be 0, i.e., Q = 0. Therefore Qn+1= 0 or “Reset” Case 3. For S = 1 and R = 0, if the clock pulse is applied (i.e., CLK = 1), the output of NAND gate 2 becomes 1; whereas the output of NAND gate 1 will be 0. Now a 0 at the input of NAND gate 3 forces the output to be 1, i.e., Q = 1.This 1 goes to the input of NAND gate 4 to make both the inputs of NAND gate 4 as 1, which forces the output of NAND gate 4 to be 0, i.e., Q' = 0. Therefore the finally the output of NAND gate 3 becomes 1. Hence Therefore Qn+1= 1 or “Set” Case 4. For S = 1 and R= 1, if the clock pulse is applied (i.e., CLK = 1), the outputs of both NAND gate 2 and NAND gate 1 becomes 0. Now a 0 at the input of both NAND gate 3 and NAND gate 4 forces the outputs of both the gates to be 1, i.e., Q = 1 and Q' = 1. Therefore an output of both the gates is equal and it is invalid or undefined. N B Navale College of Engineering, Solapur 4

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