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Schematic 3 source: linuxtoys.org Kuruvilla Varghese VHDL Features 4 • Entity – Interface Specifications • Architecture – Functionality e.g. 4 bit comparator • Function a(3) b(3) a b = equals a(2) b(2) equals a(1) b(1) a(0) b(0) Function Kuruvilla Varghese 2

Equality Comparator -- 4 bit equality comparator library ieee; use ieee.std_logic_1164.all; 5 bit - ‘0’, ‘1’ std_logic – ‘0’, ‘1’, ‘Z’, … in entity eqcomp is port (a, b: in std_logic_vector(3 downto 0); equals: out std_logic); end eqcomp; architecture arch_eqcomp of eqcomp is begin equals <= ‘1’ when (a = b) else ‘0’; end arch_eqcomp; buffer out inout buffer – has restrictions, we use signals (wires) for local feedback Kuruvilla Varghese Equality Comparator • Comments start with -- anywhere on the line • Library Packages Components, Functions, Procedures, Data Objects • Mode – in, out, inout, buffer 6 • Identifiers – Alphabetic, Numeric or underscore characters – Not case sensitive – The first character must be an alphabet – The last character cannot be an underscore – Two underscores in succession are not allowed • Range: downto, to (MSbit, LSbit) – Bit order, Byte order (Little Endian, Big Endian) Kuruvilla Varghese 3

Syntax, Operators • Architecture Body – Architecture declaration • • • • • Component declarations Type declarations Constant declarations Signal declarations Function, Procedure definitions 7 • Logical Operators – and, nand, or, nor, xor, xnor, not These are defined for data type “bit” and “boolean” For “std_logic” data type these operators are overloaded in “ieee.std_logic_1164” package – Architecture statement Kuruvilla Varghese Operators • Arithmetic Operators – +, -, *, / – ** (exponentiation) – mod (modulo division) – rem (modulo remainder) – abs (absolute value) A mod B = A – B * N A rem B = A − A / B ∗ B 8 • These operators are defined for “integer” and “real” data types • For “std_logic” data type, these operators are overloaded in “ieee.std_logic_unsigned” package Kuruvilla Varghese 4

Operators • Relational Operators =, >, <, <=, >=, /= These operators are defined for “integer” and “real” data types For “std_logic” data type, these operators are overloaded in “ieee.std_logic_arith” package 9 • Shift Operators sll (shift left logical), srl sla (shift left arithmetic), sra rol (rotate left), ror These operators are defined for “bit” and “boolean” data types For “std_logic” data type, these operators are overloaded in “ieee.std_logic_arith” package Kuruvilla Varghese Operators • Aggregate operator Applied to elements of same type and size signal a, b, c: std_logic; signal tmp: std_logic_vector(2 downto 0); tmp <= (a, b, c); 10 • Concatenation operator Concatenate different size arrays of the same element type. type byte is array (7 downto 0) of bit; signal count: byte; count <= “010” & “00110”; Kuruvilla Varghese 5

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