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Note for VHDL Programming - VHDL By ramji dr

  • VHDL Programming - VHDL
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VAAGDEVI COLLEGE OF ENGINEERING Autonomous Bollikunta, Warangal Department of Electronics & Communication Engineering VHDL Programms

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Realization of Logic Gates in VHDL  AND  OR  NAND  NOR  NOT  XNOR

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AND GATE REALISATION Program: AND Gate Behavior Level Design in VHDL -- *** AND Gate Behavior Level Design library ieee; use ieee.std_logic_1164.all; entity my_andbehavior is port (a,b: in std_logic; y:out std_logic); end my_andbehavior; architecture my_andbehavior of my_andbehavior is begin process(a,b) begin if(a = '1') then if (b = '1') then y <= '1'; else y <='0'; end if; else y <= '0'; end if; end process; end my_andbehavior; AND Gate in Data flow Level Design in VHDL library ieee; use ieee.std_logic_1164.all; entity my_andgate is port (a,b : in std_logic; y : out std_logic); end my_andgate; architecture my_andgatearch of my_andgate is begin y <= a and b after 0.5 ns; end my_andgatearch; *** --

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AND Gate Structure Level Design library ieee; use ieee.std_logic_1164.all; entity my_npinandstruct is port ( a : in std_logic_vector(0 to 3); y : out std_logic); end my_npinandstruct; architecture my_npinandstructarch of my_npinandstruct is component my_andgate port (a,b : in std_logic; y : out std_logic); end component; signal temp : std_logic_vector(0 to 1); begin a0 : my_andgate port map ( a(0), a(1), temp(0)); a1 : my_andgate port map ( a(2), temp(0), temp(1)); a2 : my_andgate port map ( a(3), temp(1), y); end my_npinandstructarch; 3 inputs AND Gate Design in VHDL -- *** 3 i/p AND Gate in Dataflow Level Design library ieee; use ieee.std_logic_1164.all; entity my_npinandbehavior is port (a,b,c : in std_logic; y : out std_logic); end my_npinandbehavior; architecture my_npinandarch of my_npinandbehavior is begin y <= a and b and c ; end my_npinandarch; *** --

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