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VLSI Design Flow, Fabrication Technology,CMOS Process Flow,Design Rules,Layout Design.
MOS Device model with sub-microne effect, VTC Parameter, CMOS Propagation delay,Layout of an Inverter,RC Delay Model,The Elmore Delay
Static CMOS logic Circuit,Ratioed logic,DC Characteristics,Pass-Transistor logic,Complementary Pass Transistor logic,Transmission Gate logic,DCVS logic,Dynamic CMOS logic circuit,Sequential logic circuits,Static Latches and Registers,SR Flip-Flop,Multiplexer Based latches,Master-Slave Based Edge Triggered Resister
Pulse based Register, sense amplifier Based Register, semiconductor Memories,Flash Memories
SRAM,CMOS SRAM Cell,CMOS SRAM Cell design,Read Operation, Write Operation,Write Circuit,DRAM,Semiconductor ROMs,NAND Based ROM Array
Hardware Description Language:VHDL
Defects, Fault Models,Design strategies for testing,Chip level and system level test Techniques,Packing Technology