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Lab Manual for DIGITAL DESIGN THROUGH VERILOG HDL - DDTV by GUGULOTH SURENDAR

  • DIGITAL DESIGN THROUGH VERILOG HDL - DDTV
  • Practical
  • Electronics and Communication Engineering
  • B.Tech
  • 306 Views
  • 14 Offline Downloads
  • Uploaded 1 year ago
Guguloth Surendar
Guguloth Surendar
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VERILOG HDL LAB MANUAL EXPERIMENT NO: 01 INTRODUCTION - XILINX Xilinx ISE is a software tool produced by Xilinx for synthesis and analysis of HDL designs, which enables the developer to synthesize ("compile") their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer.In our Lab, the scope is limited to design and analyze the design using test benches & simulation. The following is the step by step procedure to design in the Xilinx ISE: 1. New Project Creation Once the Xilinx ISE Design suite is started, open a new project & enter your design name and the location path. By default ‘HDL’ is selected as the top-level source type. (If not, please select Top-level source type as ‘HDL’) Dept. of ECE,MIST POLYTECHNIC Page 1

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VERILOG HDL LAB MANUAL 2.Continue to the next window and check if the Preferred Language is selected as ‘Verilog’ 3. Proceed by clicking ‘Next’ and create a ‘New Source’ using the ‘Create New Source’ Window Dept. of ECE,MIST POLYTECHNIC Page 2

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VERILOG HDL LAB MANUAL 4. Select the source type as ‘Verilog Module’ and input a filename and proceed to ‘Next’. In the next window ‘Define Module’ enter the ports. Dept. of ECE,MIST POLYTECHNIC Page 3

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VERILOG HDL LAB MANUAL 5. Finish with the New project setup with the ‘Summary’ window. Dept. of ECE,MIST POLYTECHNIC Page 4

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