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DIGITAL DESIGN THROUGH VERILOG HDL

by Siddalingesh Gudikeri
Type: PracticalInstitute: Visvesvaraya Technological University VTU Specialization: Electronics and Communication EngineeringOffline Downloads: 6Views: 94Uploaded: 8 months agoAdd to Favourite

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DIGITAL DESIGN THROUGH VERILOG HDL by Siddalingesh Gudikeri

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Siddalingesh Gudikeri
Siddalingesh Gudikeri

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Siddalingesh Gudikeri
Siddalingesh Gudikeri
Dep of IT STAFF NAME : Siddalingesh.G HDL MANUAL INDEX SL.NO EXPERIMENT TITLE PAGE NO PART-A 1. Write the HDL code to realize all logic gates. 2 2. Write the HDL code for the following combinational designs. a.Write the HDL code to realize 2 to 4 Decoder. 4 b.Write the HDL code to realize 8 to 3 Encoder(with and without priority). c.Write the HDL code to realize 8 to 1 Multiplexer. 6 d.Write the HDL code to realize 4-bit Binary to Gray converter. 12 e. Write the HDL code to realize 1 to 8 Demultiplexer. 14 f. Write the HDL code to realize 1-bit and 4-bit comparator. 16 20 4. Write the HDL code to describe the function of Full Adder using three modeling styles. ALU. 5. Write the HDL codes for the following flip flops:SR, JK, D, T. 28 6. Design 4 bit binary, BCD counters(Synchronous reset and Asynchronous reset) and “any sequence counters”. 36 3. 10 26 PART-B 1. 45 3. write HDL code to generate different waveforms(Sine, Square, Triangle, Ramp) using DAC to change frequency and amplitude. Write the HDL code to display numerical digits using Hex keypad input data (Keymatrix). write HDL code to control speed, direction of DC and stepper motor. 4. Test counter for interfacing programs. 57 CPLD pin assignments. 58 Execution Procedure. 59 2. R.Y.M.E.C 51 54 1
Dep of IT STAFF NAME : Siddalingesh.G HDL MANUAL PART-A Experiment No. 1 Aim: Write VHDL and verilog codes to realize all the logic gates. VHDL Code library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity gates is port ( ain, bin : in std_logic; op_not, op_and, op_or : out std_logic; op_nand, op_nor : out std_logic; op_xor, op_xnor: out std_logic ); end gates; architecture logic_gates of gates is begin op_not<= not ain; op_and<= ain and bin; op_or<= ain or bin; op_nand<= ain nand bin; op_nor<= ain nor bin; op_xor<= ain xor bin; op_xnor<= ain xnor bin; end logic_gates; 2 R.Y.M.E.C
Dep of IT STAFF NAME : Siddalingesh.G HDL MANUAL Verilog Code module (ain, bin, op_or, op_and, op_not, op_xor, op-xnor, op_nand, op_nor); input ain, bin; output op_or, op_and, op_not, op_xor, op-xnor, op_nand, op_nor; assign assign assign assign assign assign assign op_or = ain|bin; op_and = ain & bin; op_not = ain ~ bin; op_xor = ain ^ bin; op_xnor =( ain ^ bin); op_nand =( ain & bin); op_nor = (ain | bin); endmodule; 3 R.Y.M.E.C
Dep of IT STAFF NAME : Siddalingesh.G HDL MANUAL Experiment No. 2 Aim: Write VHDL and verilog codes for the following combinational designs. 2 to 4 decoder. a.VHDL code for 2 to 4 decoder. library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity DECODER is Port ( DIN : in std_logic_vector(1 downto 0); DOUT : out std_logic_vector(3 downto 0)); end DECODER; architecture Behavioral of DECODER is begin process(DIN) begin case DIN is when "00" when "01" when "10" when "11" when others end case; end process; => => => => => DOUT <= DOUT <= DOUT <= DOUT <= null; "0001"; "0010"; "0100"; "1000"; end Behavioral; 4 R.Y.M.E.C

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