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# Lab Manuals for Computer Organization - CO By K Sanath Kumar

• Computer Organization - CO
• Practical
• JNTU - JNTU
• Computer Science Engineering
• 4710 Views
K Sanath Kumar
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COMPUTER ORGANIZATION LAB DEPARTMENT OF ECE EXPERIMENT NO:1 REALISATION OF LOGIC GATES USING NAND AND NOR Aim:1) Study of logic gates using IC’s & discrete components. 2) Realization of basic gates using NAND & NOR gates (Universal gates). Apparatus: 1. Logic gates (IC) trainer kit. 2. Trainer kit for discrete circuit of gates 3. Connecting patch chords. I.Verifying the logic gates using IC’s: S.NO 1. 2. GATE NAND IC 7400 NOR IC 7402 SYMBOL A B A B 3. EX-OR IC 7486 A B C= AB C= A B INPUTS A B 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 OUTPUT C 1 1 1 0 1 0 0 0 0 1 1 0 REALIZATION OF ALL BASIC GATES USING UNIVERSAL GATE: REALIZATION OF ALL BASIC GATES USING NAND GATE: THEORY: NAND gate is actually a combination of two logic gates: AND gate followed by NOT gate. So its output is complement of the output of an AND gate. This gate can have minimum two inputs, output is always one. By using only NAND gates, we can realize all logic functions: AND, OR, NOT, X-OR, X-NOR, NOR. So this gate is also called universal gate. GURU NANAK INSTITUTE OF TECHNOLOGY Page 1

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COMPUTER ORGANIZATION LAB DEPARTMENT OF ECE i)NAND gates as NOT gate A NOT produces complement of the input. It can have only one input, tie the inputs of a NAND gate together. Now it will work as a NOT gate. Its output is Y = (A.A)’ Y = (A)’ ii) NAND gates as AND gate A NAND produces complement of AND gate. So, if the output of a NAND gate is inverted, overall output will be that of an AND gate . Y = ((A.B)’)’ Y = (A.B) iii) NAND gates as OR gate From DeMorgan’s theorems: (A.B)’ = A’ + B’ (A’.B’)’ = A’’ + B’’ = A + B So, give the inverted inputs to a NAND gate, obtain OR operation at output. GURU NANAK INSTITUTE OF TECHNOLOGY Page 2

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COMPUTER ORGANIZATION LAB DEPARTMENT OF ECE iv) NAND gates as X-OR gate The output of a to input X-OR gate is shown by: Y = A’B + AB’. This can be achieved with the logic diagram shown in the left side. Gate No. Inputs Output 1 A, B (AB)’ 2 A, (AB)’ (A (AB)’)’ 3 (AB)’, B (B (AB)’)’ 4 (A (AB)’)’, (B (AB)’)’ A’B + AB’ Now the ouput from gate no. 4 is the overall output of the configuration. = ((A (AB)’)’ (B (AB)’)’)’ Y Y = (A(AB)’)’’ + (B(AB)’)’’ = (A(AB)’) + (B(AB)’) = (A(A’ + B)’) + (B(A’ + B’)) = (AA’ + AB’) + (BA’ + BB’) = ( 0 + AB’ + BA’ + 0 ) = AB’ + BA’ = GURU NANAK INSTITUTE OF TECHNOLOGY AB’ + A’B Page 3

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COMPUTER ORGANIZATION LAB DEPARTMENT OF ECE v) NAND gates as X-NOR gate X-NOR gate is actually X-OR gate followed by NOT gate. So give the output of X-OR gate to a NOT gate, overall ouput is that of an X-NOR gate. Y = AB+ A’B’ vi) NAND gates as NOR gate A NOR gate is an OR gate followed by NOT gate. So connect the output of OR gate to a NOT gate, overall output is that of a NOR gate. Y = (A + B)’ REALIZATION OF ALL BASIC GATES USING NOR GATE: THEORY: GURU NANAK INSTITUTE OF TECHNOLOGY Page 4