MATRUSRI ENGINEERING COLLEGE SAIDABAD, HYDERABAD – 500 059 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING Name of the faculty: K. ARUNA Department: ECE Subject: DIGITAL SYSTEM DESIGN WITH VERILOG HDL Class: BE III/IV I-SEM -2017-18 COURSE OBJECTIVES 1. To understand the constructs and conventions of the Verilog HDL programming. 2. To understand the dataflow, structural, behavioral, register-transfer level (RTL) and switch levels of abstraction for modeling digital hardware systems. 3. Develop Verilog HDL code for digital arithmetic circuits using Data flow, Gate level Hierarchical structural modeling, Behavioral and Switch level modelling styles. 4. Develop Test-benches for the above models. 5. To design and modeling of combinational and sequential digital systems (Finite State Machines). 6. To understand the basic building blocks of Algorithmic State Machine (ASM) chart & to prepare ASM Chart for binary multiplier and Vending-Machine Controller. COURSE OUTCOMES 1. Able to understand the basic building blocks of the Verilog Hardware Description Language (HDL). 2. Able to design and develop program codes for Gate level, Hierarchical structural and Data flow modeling of combinational and sequential logic using Verilog HDL in any problem identification, formulation and solution. 3. Able to design and develop program codes for Switch level modeling using Verilog HDL and develop program codes for behavioral modeling of combinational and sequential logic using Verilog HDL in any problem identification, formulation and solution. 4. Able to design the Finite State Machines (FSMs) for completely specified and incompletely specified Synchronous Sequential machines. 5. Able to design the Algorithmic State Machines (ASMs) using data path and control subsystem for various Asynchronous Sequential machines. 6. Able to design combinational circuits using various PLD’s and design of memory devices, ASIC’s, FPGA’s and CPLD’s using logic gates.
MATRUSRI ENGINEERING COLLEGE SAIDABAD, HYDERABAD – 500 059 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING Lesson Plan Name of the faculty: K. ARUNA Department: ECE Class: BE III/IV I-SEM Subject: DIGITAL SYSTEM DESIGN WITH VERILOG HDL Session No. 1 2 3 4 5 6 7 8 9 Date 13.07.2017 13.07.2017 14.07.2017 17.07.2017 20.07.2017 20.07.2017 21.07.2017 24.07.2017 27.07.2017 10 27.07.2017 11 12 13 14 15 16 28.07.2017 03.08.2017 03.08.2017 04.08.2017 07.08.2017 10.08.2017 17 18 10.08.2017 11.07.2017 19 20 21 22 23 17.07.2017 17.07.2017 18.08.2017 21.08.2017 24.08.2017 24 25 26 27 24.08.2017 28.08.2017 31.08.2017 01.09.2017 28 04.09.2017 Unit No. I II Planned Topic Introduction to HDLs, Overview of Digital Design with Verilog HDL Basic Concepts, Data types System tasks and Compiler Directives Gate level Modeling Hierarchical structural modeling Dataflow modeling, Continuous Assignments Timing and Delays Programming Language Interface Design of Arithmetic Circuits - Using Vectored Signals, Using a Generic Specification Nets and Variables, Arithmetic Assignment Statements, Representation of Numbers in Verilog Code Gate level and hierarchical modeling of 4-bit Binary Adder Gate level and hierarchical modeling of 4-bit BCD adder Gate level and hierarchical modeling of 8-bit Comparator Verification: Functional verification simulation types, Design of stimulus block Review, Examples & Assignment evaluation Switch Level Modeling and examples Behavioral Modeling: Structured Procedures, Procedural Assignments Timing Controls, Conditional Statements multi-way branching, Loops Sequential and Parallel blocks, Generate blocks Tasks, and Functions Behavioral/dataflow modeling of basic MSI combinational logic modules: ALUs, Encoders Decoders, Multiplexers, Demultiplexers Parity generator/checker circuits, Bus Structure Reaction Timer Static timing analysis, Logic synthesis and Register Transfer Level (RTL) Code Review, Examples & Assignment evaluation
29 07.09.2017 III Behavioral/dataflow modeling of sequential logic modules: Latches, Flip Flops counters and shift registers Synchronous Sequential Circuits: Analysis and synthesis of synchronous sequential circuits: Mealy and Moore FSM models for completely and incompletely specified circuits MID I Test evaluation State Minimization - Partitioning Minimization Procedure sequence detector, One-Hot Encoding Synthesizable Verilog HDL models for sequence detector using Moore and Mealy models Design of a Modulo-8 Counter using the Sequential Circuit Approach and its verilog implementation FSM as an Arbiter Circuit Review, Examples & Assignment evaluation 30 31 07.09.2017 08.09.2017 32 33 34 35 14.09.2017 14.09.2017 15.09.2017 18.09.2017 36 21.09.2017 37 38 21.09.2017 22.09.2017 39 05.10.2017 IV Algorithmic State Machines (ASMs): ASM chart, ASM block, simplifications and timing considerations with design example ASMD chart for binary multiplier and Verilog HDL code one hot state controller Asynchronous Sequential logic: Analysis procedure-Transition table, flow table, race conditions Hazards with design example of Vending-Machine Controller Review, Examples & Assignment evaluation 40 41 42 05.10.2017 06.10.2017 09.10.2017 43 44 12.10.2017 12.10.2017 45 46 47 48 13.10.2017 16.10.2017 19.10.2017 19.10.2017 V 30.10.2017 Memory Devices: Types of memories RAM BJT cell and 6-T MOS RAM cell, organization of a RAM Expanding word size and capacity. Introduction to ASIC’s: Full-custom, standard-cell and Gate array based ASICs SPLDs: PROM, PAL, GAL, PLA FPGA and CPLD simplified architecture and applications ASIC/FPGA Design flow, CAD tools Combinational circuit Design with Programmable logic Devices (PLDs). Review, Examples & Assignment evaluation 49 50 51 52 53 20.10.2017 23.10.2017 26.10.2017 26.10.2017 27.10.2017 54 55 56 57 58 06.11.2017 09.11.2017 09.11.2017 10.11.2017 Revision Previous question paper discussion Previous question paper discussion Class Test TOTAL = 58 .
MATRUSRI ENGINEERING COLLEGE SAIDABAD, HYDERABAD – 500 059 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING Name of the faculty: K. ARUNA Department: ECE Subject: DIGITAL SYSTEM DESIGN WITH VERILOG HDL Class: BE III/IV I-SEM ASSIGNMENTS (UNIT WISE) Assignment: I 1. 2. 3. 4. Explain system tasks and compiler directivities in verilog. Explain representation of numbers in verilog. Write a verilog module to describe 2bit comparator in dataflow modeling. Write a verilog code for the following function F(A,B,C,D)= ∑m(0,5,7,8,9,10,12,13)+∑d(1,6,11,14) in gate level model and write test bench to verify its functionality.What are the uses of PLI? Assignment: II 1. 2. 3. 4. What is RTL code with example? Explain generated block with example. Explain static timing analysis with example. Write verilog behavioural model to model 8-bit ALU with 8 instructions with test bench. Draw input and output waveforms. 5. Write a verilog code for a 4-to-16 decoder and write test bench to verify its functionality. 6. Write short notes on the following: a) Multiway Branching b) Parity generator and checker circuits Assignment: III 1. Design and write verilog code for modulo 8 counter using sequential approach use T flipflop as memory element. 2. Write a verilog code and test bench for updown counter and draw input and output waveforms. 3. Differentiate between latch and flipflop. 4. Explain difference between mealy and moore model. 5. Write a verilog model for JK Flip flop. 6. Write verilog model for D Flip flop. 7. Write short notes on Incompletely specified FSM model Assignment: IV 1. Define ASM block and explain with example. 2. Draw ASM chart for the arbiter FSM.