LAB MANUAL D.S.D.
DIGITAL SYSTEM DESIGN LAB LTP 002 CLASS WORK EXAM TOTAL DURATION OF EXAM : 25 :25 :50 :3 Hrs LIST OF EXPERIMENTS 1. Design all the gates using VHDL. 2. Write VHDL programs for the following circuits, check the waveforms generated. (a) Half-adder (b) Full-adder 3. Write VHDL programs for the following circuits, check the waveforms generated. (a) Multiplexer (b) Demultiplexer 4. Write VHDL programs for the following circuits, check the waveforms generated. (a) Decoder (b) Encoder 5. Write VHDL programs for the comparator, check the waveforms generated. 6. Write VHDL programs for the code converter, check the waveforms generated. 7. Write VHDL programs for the Flip-flop, check the waveforms generated. 8. Write VHDL programs for the counter, check the waveforms generated. 9. Write VHDL programs for the following circuits, check the waveforms generated. (a) Register (b) Shift register 10. Implement any three (given above) on FPGA/ CPLD kit.
Rational behind VHDL Lab VHDL is VHSIC (Very High Speed Integrated Circuits) Hardware Description Language .VHDL is designed to describe the behavior of the digital systems It is a design entry language .VHDL is concurrent .Using VHDL test benches, we can verify our design. VHDL integrates nicely with low level design tools. It is IEEE standard (1076 and 1164).VHDL has hierarchical design units. Learning VHDL is easy. A structure level description defines the circuit in terms of a collection of components. It is a language which provides us a mechanism to model the digital circuits without the requirement of IC’s and hardware. It enables us to write the code for the digital circuits and useful in designing of the complex VLSI’s. VHDL supports behavioral, structural descriptions, thus supporting various levels of abstraction. Hardware Requirements Pentium IV Processor 128MB RAM Software Requirements Operating System: Windows 95 Onwards Language: Active_HDL 7.2
An Introduction and Background VHDL is an acronym which stands for VHSIC Hardware Description Language. VHSIC is yet another acronym which stands for Very High Speed Integrated Circuits. If you can remember that, then you're off to a good start. The language has been known to be somewhat complicated, as its title. The acronym does have a purpose, though; it is supposed to capture the entire theme of the language, that is to describe hardware much the same way we use schematics. VHDL can wear many hats. It is being used for documentation, verification, and synthesis of large digital designs. This is actually one of the key features of VHDL, since the same VHDL code can theoretically achieve all three of these goals, thus saving a lot of effort. In addition to being used for each of these purposes, VHDL can be used to take three different approaches to describing hardware. These three different approaches are the structural, data flow, and behavioral methods of hardware description. Most of the time a mixture of the three methods is employed. The following sections introduce you to the language by examining its use for each of these three methodologies. There are also certain guidelines that form an approach to using VHDL for synthesis, which is not addressed by this tutorial. VHDL is a standard (VHDL-1076) developed by IEEE (Institute of Electrical and Electronics Engineers). The language has been through a few revisions, and you will come across this in the VHDL community. Currently, the most widely used version is the 1987 (std 1076-1987) version, sometimes referred to as VHDL'87, but also just VHDL. However, there is a newer revision of the language referred to as VHDL'93. VHDL'93 (adopted in 1994 of course) is fairly new and is still in the process of replacing VHDL'87. Descriptions To make designs more understandable and maintainable, a design is typically decomposed into several blocks. These blocks are then connected together to form a complete design. Using the schematic capture approach to design, this might be done with a block diagram editor. Every portion of a VHDL design is considered a block. A VHDL design may be completely described in a single block, or it may be decomposed in several blocks. Each block in VHDL is analogous to an off-the-shelf part and is called an entity. The entity describes the interface to that block and a separate part associated with the entity describes how that block operates. The interface description is like a pin description in a data book, specifying the inputs and outputs to the block. The description of the operation of the part is like a schematic for the block. For the remainder of the