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Solution to Previous Year Exam Questions for Switching Theory and Logic Design - STLD of BPUT by Mitu Baral

  • Switching Theory and Logic Design - STLD
  • 2016
  • PYQ Solution
  • Biju Patnaik University of Technology BPUT - BPUT
  • Computer Science Engineering
  • B.Tech
  • 113 Views
  • Uploaded 8 months ago
Mitu Baral
Mitu Baral
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Solution Prepared by Sl.No. 1 Faculty Name MITU BARAL Email ID mitubaral@gmail.com NATIONAL INSTITUTE OF SCIENCE &TECHNOLOGY PALUR HILLS, BERHAMPUR, ORISSA – 761008, INDIA

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Switching Theory & Logic Design Regular Exam-2016 B.Tech PCS3I101 PART-A 1. Answer the following question: (a) Radix of binary number system is _____? Ans: 2 (b) In the gray code, each successive code differs from its preceding code by ____. Ans: 1-bit (c) The resultant of the function cannot be further simplified is called___ (i) Minimal (ii) Irredundant (iii) Both(i) or (ii) (iv) None Ans: (iii) Both(i) or (ii) (d) 1+A+AB+ABC+........ = _______. Ans: 1 (e) In an n-variable K-Map, each cell contains _____number of adjacent. Ans: n (f) A carry look ahead adder is frequently used for addition, because it (i) Is faster (iii) is more accurate (ii) uses fewer gate (iv) cost less Ans: (i)Is faster (g) Which logic device is called distributor? (i) Multiplexer (ii) De-multiplexer (iii) Encoder (iv) Decode Ans: (ii) De-multiplexer (h) _______ Flip flop is widely used for data storage purpose. Ans: D-Flip Flop (i) The bit sequence 1010 is serially entered (right-most bit first) into a 4-bit parallel out shift register that is initially clear. What are the Q outputs after two clock pulses? (i) 0011 (ii) 1001 (iii) 1111 (iv)1000 Ans: (iv)1000 (j) The frequency at the MSB of a MOD-8 counter, clocked by 20 KHz clock signal is__. Ans: 2.5KHz 2. Answer the following question: (a) Determine the base of the number if 24+17=40. Ans: 24  17  40   2  r1  4  r 0   1 r1  7  r 0    4  r1  0  r 0    2r  4   r  7   4r  r  11 (Base) (b) Convert (41.6875)10 into binary number. Ans: (41.6875)10=(101001.1011)2 National Institute of Science and Technology, Berhampur-761008 Page 2

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Switching Theory & Logic Design Regular Exam-2016 B.Tech PCS3I101 (c) Find the complement and dual of the expression. F  x(y 'z' yz) . Ans: Complement: F'  x ' (y  z)(y' z') FD  x  (y ' z')(y z) Dual: (d) What is prime implicant in K-Map? When it is said to be essential? Ans:  A prime implecant is a product term which can be obtained by combining maximum possible number of adjacent groups.  A prime implecant is called an essential prime implecant if it is not covered by another overlapping group. (e) How can a decoder be used as demultiplexer? Ans:  The select line of demux goes to input bits of decoder.  The input pin of demux goes to „enable pin of decoder‟. (f) What is meant by priority encoder? How is it different from encoder? Ans:  If there is more than one input at logic level “1” then actual output code is only correspond to the input with the highest designated priority. Then this type of digital encoder is commonly known as a Priority Encoder.  In general encoder we cannot simultaneously provide more than one input. (g) How a D-flip flop obtained from JK flip flop? Write its truth table. Ans: (h) What is meant by storage capacity of a register? Ans: The storage capacity of a register is the total number of bits (1 or 0) of digital data it can retain. Each stage (flip flop) in a shift register represents one bit of storage capacity. Therefore the number of stages in a register determines its storage capacity. National Institute of Science and Technology, Berhampur-761008 Page 3

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Switching Theory & Logic Design Regular Exam-2016 B.Tech PCS3I101 (i) Distinguish between static and dynamic hazards. Ans:  Static Hazards It is a condition which results in a single  Dynamic Hazards The output changes more than once as a momentary incorrect output due to the result of a single input change. Dynamic change in input variable, when the hazards are occurring in multiple level output is expected to remain in the same circuits. state.   It is also called as glitch. It is also called a bounce (j) When two states are said to be equivalent? Ans: Two states are said to be equivalent if each member of set of inputs they give exactly the same outputs and send the circuit either to the same state or to an equivalent state. PART-B 3. (a) Briefly explain about error detection and correction code. A transmitter uses a single error correcting code for the message using even parity. The message received at the receiving end is 1110101. Check and correct the error. Ans:  The main principle used in constructing error detection code is to use redundant bits in codes with the specific purpose of detecting errors.  One common method of constructing such codes is the introduction of an extra bit in the code. This bit is called parity bit.  If the code word includes odd number of 1‟s including parity bit is called odd parity where as if number of 1‟s is even including parity bit is called even parity. National Institute of Science and Technology, Berhampur-761008 Page 4

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