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- Switching Theory and Logic Design - STLD
- 2017
- PYQ
**Biju Patnaik University of Technology Rourkela Odisha - BPUT**- Computer Science Engineering
- B.Tech
**30116 Views**- 451 Offline Downloads
- Uploaded 1 year ago

Registration No: Total Number of Pages: 03 B.Tech. PCS3I101 3rd Semester Regular/Back Examination 2017-18 SWITCHING THEORY AND LOGIC DESIGN BRANCH : CSE Time : 3 Hours Max Marks : 100 Q.CODE : B889 Answer Question No.1 and 2 which are compulsory and any four from the rest. The figures in the right hand margin indicate marks. Q1 a) b) c) d) e) f) Answer the following questions: multiple type or dash fill up type How many inputs of a four-input AND gate must be HIGH in order for the output of the logic gate to go HIGH? A.any one of the inputs B.any two of the inputs C.any three of the inputs D.all four inputs One of De Morgan's theorems states that Simply stated, this means that logically there is no difference between: A.a NOR and an AND gate with inverted inputs B.a NAND and an OR gate with inverted inputs C.an AND and a NOR gate with inverted inputs D. a NOR and a NAND gate with inverted inputs How many gates would be required to implement the following Boolean expression before simplification? XY + X(X + Z) + Y(X + Z) A.1 B.2 C.4 D.5 Before an SOP implementation, the expression would require a total of how many gates? A.1 B.2 C.4 D.5 On the fifth clock pulse, a 4-bit Johnson sequence is Q0 = 0, Q1 = 1, Q2 = 1, and Q3 = 1. On the sixth clock pulse, the sequence is ________. A.Q0 = 1, Q1 = 0, Q2 = 0, Q3 = 0 B.Q0 = 1, Q1 = 1, Q2 = 1, Q3 = 0 C.Q0 = 0, Q1 = 0, Q2 = 1, Q3 = 1 D.Q0 = 0, Q1 = 0, Q2 = 0, Q3 = 1 Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz. A.10.24 kHz B.5 kHz C.30.24 kHz D.15 kHz (2 x 10)

g) h) i) j) Q2 a) b) c) d) e) f) g) h) i) j) Q3 a) b) A MOD-16 ripple counter is holding the count 10012. What will the count be after 31 clock pulses? A.10002 B.10102 C.10112 D.11012 If two inputs are active on a priority encoder, which will be coded on the output? A.the higher value B.the lower value C.neither of the inputs D.both of the inputs How many 74184 BCD-to-binary converters would be required to convert two complete BCD digits to a binary number? A.8 B.4 C.2 D.1 A carry look ahead adder is frequently used for addition, because it A. Is faster B. is more accurate C. uses fewer gate D. cost less Answer the following questions: Short answer type What are the universal gates? Why they are called universal gate? What are the differences of flip-flop and Latch? Convert the following. 97710 = ( )16 How a D-flip flop obtained from JK flip flop? Write its truth table. Convert the given expression in canonical SOP form y=AC+AB+BC. What is edge-triggered flip-flop? What is race around condition? What are the applications of shift registers? What is the basic type of counter made by flip-flop or resistor? Distinguish between static and dynamic hazards. (2 x 10) Minimize the following function using K-map and also verify through tabulation method. F (A, B, C, D) = ∑m(1,4,5,7,8,9,12,14)+d (0, 3, 6, 10). Reduce the following Boolean expression using Demorgan’s theorems. AB+A (B+C) +Bˈ(B+D) (10) (5) Q4 a) b) Design BCD to gray code converter and realize using logic gates. Why a multiplexer is called a data selector? Draw the 2x1 MUX. (10) (5) Q5 a) Given the 8bit data word 01011011, generate the 12 bit composite word for the hamming code that corrects and detects single errors. Design half adder from 2 to 4 decoder (10) b) (5)

Q6 a) b) Explain the operation of 5-stage twisted ring counter with circuit diagram, state transition diagram and state table. Draw the circuit of J – K master slave flip-flop with active high clear and active low preset. (10) (5) Q7 a) b) Define an encoder. Design octal to binary encoder. Differentiate between an ASM chart and a conventional flow chart? (10) (5) Q8 a) Draw the logic diagram of a SR latch using NOR gates. Explain its Operation usingexcitation table. Write the difference between combinational circuit and sequential circuit (10) What is a shift register? Draw the block diagram and timing diagram of a shift register that shows the serial transfer of information from register A to register B. Implement the following functions using NAND gates. a) F1= A (B+C D) + (B C)ˈ (10) b) Q9 a) b) (5) (5)

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