Previous Year Exam Questions of Basic Electronics of BPUT - BE by Verified Writer
- Basic Electronics - BE
- 2017
- PYQ
- Biju Patnaik University of Technology Rourkela Odisha - BPUT
- Computer Science Engineering
- B.Tech
- 15102 Views
- 430 Offline Downloads
- Uploaded 1 year ago
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Registration No: Total Number of Pages : 02 B.Tech. 15BE2101 1st Semester Back Examination 2017-18 BASIC ELECTRONICS BRANCH: AERO, CHEM, CIVIL, CSE, ECE, EEE, ELECTRICAL, ETC, IT, MECH, MME, PE, PLASTIC, TEXTILE Time: 3 Hours Max Marks: 100 Q.CODE: B999 Answer Question No.1 and 2 which are compulsory and any four from the rest. The figures in the right hand margin indicate marks. Q1 (2 x 10) j) Answer the following questions: multiple type or dash fill up type The thermal runaway in a CE transistor amplifier can be prevented by biasing the transistor in such a manner that a) VCE> VCC/2 b) VCE< VCC/2 c) VCE = VCC/2 d) VCE=0 A diode is said to be useful to be configured as an amplifier when its β is a) Less than 0 b) between 0 & 1 c) between 1 & 50 d) > 50 A full wave rectifier needs at least --------- diodes. The maximum efficiency of an half wave rectifier is ------------- %. The frequency compensation is used in Op-Amps to increase its ----------------. An Instrumentation amplifier uses ------------- Op-Amps. Which of the following is not associated with a p-n junction a) junction capacitance b)charge storage capacitance c) depletion capacitance d) channel length modulation 9’s complement of 68 is -----------The decimal equivalent of 10010111 is ------What is mean by PIV rating of a diode a) Maximum reverse bias potential which can be applied across a diode without breakdown b) Maximum forward bias potential which can be applied across a diode without breakdown c) Minimum potential required by a diode to reach conduction state d) Maximum power allowable to a diode SR Flip flop can be converted to T-type flip-flop if …………… Answer the following questions: Short answer type Define CMRR and Slew rate. Difference between zener breakdown and avalanche breakdown. Derive the relation between . Prove Demorgan’s Theorem. Draw the IEEE logic symbol of AND, NOT, NOR & XOR gates. Define Bark Hausen criterion. Give the relationship between ICO& ICEO. Define the thermal runaway of transistor. What is common collector configuration of BJT ? (2 x 10) a) b) c) d) e) f) g) h) i) a) b) c) d) e) f) g) h) i) Q2
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j) What is input impedance of op-amp circuit in the above figure? Q3 a) With neat circuit diagram and waveforms, explain the working of a full wave bridge rectifier. Also discuss the PIV for center tapped Transformer. b) (10) (5) Discuss the above circuit with sinusoidal input of peek to peek voltage 10 V, VR1 = 2V, VR2 = 1V, R= 1Ω, and the diode are silicon diodes Q4 a) b) Q5 a) b) Q6 a) b) Q7 a) b) Q8 a) b) Q9 a) b) The i/p to the Full wave rectifier is v(t) = 200 sin50t. If RL is 1kΩ and forward resistance of diode is 50Ω, find: D.C current through the circuit The A.C (rms)value of current through the circuit The D.C output voltage The A.C power input The D.C power output Rectifier efficiency. Explain zener diode voltage regulator circuit with no load and with load. (10) With a neat circuit diagram, explain the Voltage Divider Bias circuit using approximate analysis. Also derive the equation of stability (S) for Voltage Divider Bias circuit. What is a DC load line? Explain Base biased method with necessary equations. (10) Design a single stage common source amplifier for following specification. Av= 25, V0= 2.5 V Derive the expression of 3 input summing amplifier. (10) Convert (1101101)2= ( )10 and (69)10= ( )2 Convert (1010111011110101)2= ( )16 and (FA876)16= ( )2 Write notes on Universal Gates. Also realize NOR using NAND gates only. (10) Factories the following Boolean equations Y1=AB’+AB Y2= (B+CA) + (C+A’B) Write a note on Full Adder. What is a RS Flip-Flop? Explain using its circuit diagram, logic symbol and truth table. (10) Write the principle and working of CRO with proper block diagram. Write notes on Virtual ground Clamper circuit (10) (5) (5) (5) (5) (5) (5)
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