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Previous Year Exam Questions of Advanced Computer Architecture of bput - ACA by Verified Writer

  • Advanced Computer Architecture - ACA
  • 2017
  • PYQ
  • Biju Patnaik University of Technology Rourkela Odisha - BPUT
  • Computer Science Engineering
  • B.Tech
  • 17001 Views
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  • Uploaded 1 year ago
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Registration No : Total Number of Pages : 02 B.Tech PCS5I001 5th Semester Regular Examination 2017-18 Advanced Computer Architecture BRANCH : CSE Time : 3 Hours Max Marks : 100 Q. CODE : B310 Answer Question No.1 and 2 which are compulsory and any four from the rest. The figures in the right hand margin indicate marks. Q1 a) b) c) d) e) f) g) h) i) j) Q2 a) b) c) d) e) f) g) h) i) j) Q3 a) b) Q4 a) b) Answer the following questions: multiple type or dash type 80386 Microprocessor is ____bit processor. In Super Scalar architecture instruction scheduling is i)Static ii) Dynamic iii) Hybrid iv) Pseudostatic Array Processor is i)SISD ii) MISD iii) SIMD iv) MIMD The number of Control Units in Vector Processor is i)one ii) two iii) four iv) n Bisection width of N X N mesh network is ______. The number of switches required for N X N Dynamic network is______. Type of memory used in set-associative cache is i)Static ii) Dynamic iii) Associative iv) Pseudostatic The technique used in Virtual memory is i)paging ii) segmentation iii) either (i) or (ii) iv) both (i) and (ii) Type of control unit used in RISC is i)Hard-wired ii) Soft-wired iii) Microprogrammed iv) both (i) and (ii) Memory bus is i)Synchronous ii) Asynchronous iii) Semi-synchronous iv) both (i) and (ii) (2 x 10) Answer the following questions: Short answer type What do you mean by Spatial and Temporal locality of reference? What is Flynn’s classification? What do you mean by Cache coherence? What do you mean by Address space? Whether for single instruction execution non-pipeline system is better than pipeline system? Justify. What do you mean by Distributed memory system? How many Floating point registers are there in the Floating Point Unit of SPARC? How overlapped CPU and I/O operations are performed in computer system? Explain with example. State Amdahl’s low and explain. To multiply 18 by -1, if 18 is in source, how many cycles needed by ARM? (2 x 10) Assume a cache miss penalty is 100 clock cycles, and all instructions take 1.0 clock cycles. Let the average miss rate is 2%, there is an average of 1.5 memory references per instructions, and the average number of cache misses per 1000 instructions is 30. What is the impact on the performance and calculate the impact using both misses per instruction and miss rate? What are the writing policies of Cache? Explain with diagram. (10) What do you mean by Speed-Up of pipeline? Derive equations of Speed-Up and Efficiency for Pipeline, Super pipeline and Super scalar architecture. What is a SPARC processor? What are the modules in SPARC? Explain each. (8) (5) (7)

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Q5 a) b) Q6 a) b) c) Q7 a) b) Q8 a) b) Q9 a) b) c) d) What is a Pipeline Hazard? How control hazard is detected and resolved? Explain with example. What is THUMB? How THUMB instructions are executed by ARM? Is it advantageous? Distinguish and Differentiate. UMA Vs. NUMA RISC Vs. CISC Super scalar architecture Vs. VLIW architecture (10) (5) (5) (5) (5) What is Interconnection network? Draw a Shuffle network and explain the communication mechanism. Whether array processor is same as vector processor? Justify your answer. (10) What is virtual memory? How a logical address is mapped to physical address in virtual concept? Explain with example and diagram. What are the page replacement algorithms are used in virtual memory? Explain each. (10) Write Short Notes on any THREE. Distributed memory system I/O subsystem Cloud computing Microcontroller (5) (5) (5 x 3)

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