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Previous Year Exam Questions for Advanced Computer Architecture - ACA of 2017 - bput by Verified Writer

  • Advanced Computer Architecture - ACA
  • 2017
  • PYQ
  • Biju Patnaik University of Technology Rourkela Odisha - BPUT
  • Computer Science Engineering
  • B.Tech
  • 6744 Views
  • 174 Offline Downloads
  • Uploaded 1 year ago
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Registration No: Total Number of Pages : 01 B.Tech. PECS5404 7th Semester Regular/Back Examination 2017-18 Advanced Computer Architecture BRANCH : CSE Time : 3 Hours Max Marks : 70 Q. CODE : B354 Answer Question No.1 which is compulsory and any five from the rest. The figures in the right hand margin indicate marks. Q1 a) b) c) d) e) f) g) h) i) j) Q2 a) b) Q3 a) b) Q4 a) b) Q5 (2 x 10) A computer where the clocks per instruction is 1.0 when all memory accesses hit in the cache. The only data accesses are loads and stores, and these total 50% of the instructions. If the miss penalty is 25 clock cycles and the miss rate is 2%, how much faster would be the computer is if all instructions were cache hits? What is THUMB? How THUMB instructions are executed by ARM? Is it advantageous? (6) What is Super scalar architecture? Is it faster than Super pipeline architecture? Draw a Time-Space diagram for comparison. What do you mean by Speed-Up of pipeline? Derive equations of Speed-Up and Efficiency for Pipeline, Super pipeline and Super scalar architecture. (4) What is a SPARC architecture? What are the data types of SPARC? What is Interconnection network? Draw a Butterfly network and explain the communication mechanism. (5) (5) (4) (6) a) b) Distinguish and Differentiate. Array processor Vs. Vector processor I/O bus Vs. Memory bus (5) (5) a) b) Justify your answer. Whether loosely coupled multiprocessor is multicomputer? Whether ARM is RISC architecture? (5) (5) Q6 Q7 Answer the following questions: What do you mean by Spatial and Temporal locality of reference? What is a process? How is it different from thread? What do you mean by Cache coherence? What do you mean by Address space? What is Bisection width of an interconnection network? What do you mean by Distributed memory system? What type of Control unit is used in RISC processor? What is VLIW architecture? State Amdahl’s low and explain. What are the writing policies of Cache? Explain with diagram. a) b) Q8 a) b) c) What do you mean by Performance of a system? How it is measured? What is virtual memory? How a logical address is mapped to physical address in virtual concept? Explain with example and diagram. Write Short Notes on any TWO : Split Transaction bus Hyper threading RISC Vs. CISC (4) (6) (5 x 2)

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