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Previous Year Exam Questions for Digital System Design - DSD of 2017 - bput by Verified Writer

  • Digital System Design - DSD
  • 2017
  • PYQ
  • Biju Patnaik University of Technology Rourkela Odisha - BPUT
  • Electronics and Communication Engineering
  • B.Tech
  • 2140 Views
  • 71 Offline Downloads
  • Uploaded 1 year ago
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Registration No: Total Number of Pages: 02 B.TECH PET5H003 5th Semester Regular Examination 2017-18 Digital System design BRANCH : ECE, ETC Time: 3 Hours Max Marks: 100 Q.CODE: B453 Answer Part-A which is compulsory and any four from Part-B. The figures in the right hand margin indicate marks. Q1 a) b) c) d) e) f) g) h) i) j) Q2 a) b) c) d) e) f) g) h) i) j) Part – A (Answer all the questions) Answer the following questions: multiple type or dash fill up type Full adder contains ----- numbers of half adder and ------ number of OR gate? 3:1 MUX require ------ numbers of 2:1 MUX. PLA stands for ------- and PAL stands for -----------. The characteristics equation of SR flip flop is --------- and ---------. SR flip flop can be D flip flop by ---------------. Race around condition is appeared in --------- and --------- flip flop. PET stands for --------- and NET stands for --------. FPGA stands for---------- and used for -----------. Reduction of pulse width helps in -------------. The characteristics equation of JK flip flop is ----- and for T flip flop is --. Answer the following questions: Short answer type Differentiate between entity and architecture in VHDL programming? What do mean by data flow model in VHDL? Explain with examples. Define CASE statement in VHDL? How generic statement is used in VHDL? What is the use of generic key word in VHDL? Explain the user defined data types with examples? Differentiate between declaration of one dimensional array and two dimensional arrays in VHDL? How when-else and with-select statements are used in VHDL? Discuss these statements with examples. Define attribute? What are the different attribute in VHDL, gives some examples. Differentiate between for statement and while statement in VHDL, explain with examples. Write down the statements for level and edge triggering clock signals in VHDL. (2 x 10) (2 x 10)

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Part – B (Answer any four questions) Q3 a) Design the sequential detector circuit using FSM which will detect 1100. b) Write down the difference between Moore and Mealy model. (10) (5) Q4 a) With flow diagram explain about how algorithm state machine(ASM) chart can be used for describe finite state machine(FSM) with examples. b) Write down the VHDL code for 3 bit multiplier using add-shift method. (10) Q5 a) Draw and explain the circuit diagram for datapath circuit for enhanced divider. b) Write down the VHDL code for n bit parallel adder using generic declaration. (10) Q6 a) Discuss different memory elements and with proper example discuss their excitation function. b) Write down the VHDL code for 3 bit divider circuit using VHDL. (10) Q7 a) Draw the basic architecture of FPGA. And discuss in detailed the different part of FPGA. b) What do mean by behavioral design in VHDL. Write down the VHDL code for a D-flip flop using behavioral model. (10) Q8 a) Draw a state diagram for a 2-bit counter circuit. Discuss the importance of state reduction technique for this circuit. b) Differentiate between processes and generate statement in VHDL. With examples highlight the use in examples. (10) Q9 a) What do mean by hazards? How many types of hazards are found in the system, explain about them? What is the importance of hazards? b) Write a VHDL code for a 2x2 memory element. (10) (5) (5) (5) (5) (5) (5)

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