Registration no: Total Number of Pages: 03 B.TECH PEE4I103 4th Semester Regular / Back Examination 2017-18 DIGITAL ELECTRONICS CIRCUIT BRANCH(S): ELECTRICAL Time: 3 Hours Max marks: 100 Q.CODE:C772 Answer Question No.1 & Question No.2 which are compulsory and any four from the rest. The figures in the right hand margin indicate marks. Answer all parts of a question at a place. Q1 Answer the following questions: a) b) c) d) e) f) g) h) i) j) Q2 (2 x 10) The NAND gate output will be low if the two inputs are (A) 00 (B) 01 (C)10 (D) 11 A ring counter consisting of five Flip-Flops will have (A) 5 state (B) 25 states (C) (2)25 states (D) Infinite states. If the input to T-flipflop is 100 Hz signal, the final output of the three T-flipflops in cascade is (A) 1000 Hz (B) 500 Hz (C)333 Hz (D) 12.5 Hz. (734)8 = ( _____ )16 (A) C 1 D (B) D C 1 (C) 1 C D (D) 1 D C If J = K (J and K are shorted) in a JK flip-flop, what circuit is made A. SR flip-flop B. Shorted JK flip-flop C. T flip-flop D. K flip-flop A device which converts BCD to Seven Segment is called _______ (A) Encoder (B) Decoder (C) Multiplexer (D) Demultiplexer The hexadecimal number ‘A0’ has the decimal value equivalent to_______ How many Flip-Flops are required for mod-16 counter? (A) 5 (B) 6 (C) 3 (D) 4 The Boolean expression A.B’ + A’.B + A.B is equivalent to_______ The minimal function that can detect a “divisible by 3" 8421 BCD code digit (representation is D8 D4 D2 D1) is given by A. D8D1+D4D2+D’8D2D1 B. D8D1+D4D2 D’1+ D’4D2 D1+D’8 D’4D’2D’1 C. D8D1+D4D2+ D’8 D’4D’2D’1 D. D4D2 D’1+ D4D2 D1+ D8 D’4D2D1 Answer the following questions: a) 2’s complement representation of a 16 bit number (one sign bit and 15 magnitude bits) is FFFF. Represent its magnitude in decimal. b) What is race around condition? How to over come to this situation. c) Draw the flip-flop output waveforms of a 4-bit SISO shift register assuming the initial data stored in the register is 1001? (2 x 10)
d) What is the expression for the Boolean Function F in the circuit shown in the figure below? e) f) g) h) i) j) Q3 Q4 If (AB)’ + A’B= C then find (AC)’ + A’C What is priority encoder? Write the truth table of 4 input priority encoder. State the difference between edge triggering and level triggering. How many numbers of Boolean functions that can be generated by n variables? Compare the characteristics equation of R-S Flip-Flop with J-K Flip-Flop. Realize the Boolean expression Y= (x+y)(x+y’) using NAND gates. a) Design a comparator circuit that compares two ‘4’ bit Numbers A and B With all conditions. (10) b) Find the dual and complement of the following Boolean expression F(x,y,z) = (5) a) x’yz+x’yz’+xy’z’+xy’z Implement the Boolean Function ( , , , ) = ∑(1,3,4,11,13,14,15) using 4X1 MUX? b) Construct a 5-to 32-line decoder with four Nos of 3-to 8-line decoder having enable line (10) (5) and a 2- to 4-line decoder. Use block diagram for the components? Q5 Q6 Q7 a) A PN flip-flop has four operations: clear to ‘0’, no change, complement and set to ‘1’, when (8) inputs P and N are 00,01,10,11 respectively. Tabulate the characteristic table and derive the characteristic equation? b) Design a mod 4 synchronous counter using J-K Flip Flop and implement it. (7) a) With neat sketch, explain the operation of a 3-bit universal shift register b) Design a 3 x 8 decoder and Implement it using a suitable PLA. (8) a) The K - map for a Boolean function is shown in the figure below. Find out the number of (10) (7) essential prime implicants for this function? Q8 AB CD 00 01 11 10 00 1 1 0 1 01 0 0 0 1 11 1 0 0 0 10 1 0 0 1 b) With proper block diagram explain SAR type ADC (Analog to Digital Converter) (5) a) All the logic gates shown in the figure have a propagation delay of 20 ns. Let A=C=0 and (10) B=1 until time t=0. At t=0, all the inputs flip (i.e. A=C=1 and B=0) and remain in that state. For t>o. for how much duration (in ns) the output (z) will be at logic 1. Explain?
b) Explain the operation of a 8 x 1 Multiplexer and Implement the following function using a suitable Multiplexer F(A, B, C, D) = ∑m (0, 1, 3, 5, 6, 7, 8, 9, II, 13, 14) Q9 a) A 16 bit ripple carry adder is realized using 16 identical full adders (FA) as shown in the (5) (10) figure. The “carry” propagation delay of each FA is 12 ns and the “sum” propagation delay of each FA is 15 ns. Find the worst case delay (in ns) of this 16 – bit adder? b) Design an EX-OR gate using CMOS only. (5)