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Previous Year Exam Questions for VLSI Design - VLSI of 2018 - CEC by Bput Toppers

  • VLSI Design - VLSI
  • 2018
  • PYQ
  • Biju Patnaik University of Technology BPUT - BPUT
  • Electrical and Electronics Engineering
  • B.Tech
  • 8893 Views
  • 172 Offline Downloads
  • Uploaded 11 months ago
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Registration No : Total Number of Pages : 02 B.Tech. PEE6J001 6th Semester Regular Examination 2017-18 VLSI DESIGN BRANCH : EEE, ELECTRICAL Time : 3 Hours Max Marks : 100 Q.CODE : C350 Answer Part-A which is compulsory and any four from Part-B. The figures in the right hand margin indicate marks. Q1 a) b) c) d) e) f) g) h) i) j) Q2 a) b) c) d) e) f) g) h) i) j) Part – A (Answer all the questions) Answer the following questions : Which among the following is a process of transforming design entry information of the circuit into a set of logic equations? (a) Simulation (c) Synthesis (b) Optimization (d) Verification The _____________ programming technology is predominantly associated with FPGAs. In enhancement MOSFET, the magnitude of output current __________ due to an increase in the magnitude of gate potentials. (a) Increases (c) Decreases (b) Remains constant (d) None of the above Which programming technology/ies is/are predominantly associated with SPLDs and CPLDs? (a) EPROM (c) EEPROM (b) Flash (d) All the above ______________ is used in logic design of VLSI. The current IDS _______ as VDS increases. Gate capacitance per unit area is scaled by ______. In a PLA ___________ are programmable. In a BIST technique ORA and PSBRG uses ___________ The PLA provides a systematic and regular way of implementing multiple output functions of n variables in (a) POS form (c) Complex form (b) SOP form (d) Simple form Answer the following questions : Short answer type : How to calculate the fan-in and fan-out in digital electronics? What are the advantages and disadvantages of FPGAs? Draw the circuit diagram for CMOS two-input NOR Gate. Draw the basic structure of a CMOS domino logic. What is the necessity of clocked sequential circuit in VLSI design? List out the limitations of Constant Field Scaling. Compare CMOS, Bipolar Junction Transistor (BJT) and Gallium Arsenide Technology (GaAs). Give the advantages and disadvantages of cell based design and ASIC design. Why is PMOS good to pass logic 1 and NMOS is good to pass logic 0? Explain? What is the difference between LUT and CLB? (2 x 10) (2 x 10)

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Q3 a) b) Q4 a) b) Q5 a) b) Q6 a) b) Q7 a) b) Q8 a) b) Q9 a) b) Part – B (Answer any four questions) Explain the p-well CMOS Step by Step Fabrication Processing Technology with neat diagram? Compare full custom design with semi custom design styles upon the design cycle time and achievable circuit performance. (10) (5) An nMOS transistor is operating in saturation region with the following parameters. Vgs=4V, Vth=1.1V, W/L=110, µnCox=110µA/V2. Find Transconductance of the device. Explain the term “aspects of MOSFET” in VLSI Design? (10) Discuss the inverter delay and propagation delay with neat diagram and derivation? Draw the stick diagram and layout diagram for a CMOS 2 input NAND gate. (10) What is the need of Testability and explain why do we need DFT (Design For Testability) in a VLSI domain. Explain the advantages and disadvantages SoC design. (10) Explain two phase clock generator using D- flip-flop and draw the corresponding waveforms? Explain CMOS transmission gates? What do you mean by high impedance state? (10) Define threshold voltage in CMOS and derive an expression for threshold voltage of a CMOS inverter. Show the VTC and power supply current of a CMOS Inverter circuit. What is Dynamic power dissipation in CMOS? (10) Consider a CMOS inverter with the following parameters: nMOS VTO,n = 0.8v µnCox=64µA/V2 (W/L)n=8 pMOS VTO,p=-0.9v µpCox=28µA/V2 (W/L)p=12 Calculate the noise margins and the switching threshold (Vth) of this circuit. The power supply voltage is VDD=3.4V. Explain what are the five electrical parameter characterize level 1 Model equation using SPICE model? Write the SPICE keyword for the above five electrical parameter. (10) (5) (5) (5) (5) (5) (5)

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