Previous Year Exam Questions of Software Define Radio Architecture System and Function of bput - SDRASF by Bput Toppers
- Software Define Radio Architecture System and Function - SDRASF
- 2018
- PYQ
- Biju Patnaik University of Technology Rourkela Odisha - BPUT
- Electronics and Communication Engineering
- B.Tech
- 1974 Views
- 24 Offline Downloads
- Uploaded 1 year ago
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Registration No : Total Number of Pages : 02 B.Tech. PET6D001 6th Semester Regular Examination 2017-18 SOFTWARE DEFINE RADIO ARCHITECTURE SYSTEM AND FUNCTION BRANCH : ECE, ETC Time : 3 Hours Max Marks: 100 Q.CODE : C508 Answer Part-A which is compulsory and any four from Part-B. The figures in the right hand margin indicate marks. Answer all parts of a question at a place. Q1. a) b) c) d) e) f) g) Part – A (Answer all the questions) Answer the following questions: multiple type or dash fill up type : The resolution of a 0–5 V 6-bit digital-to-analog converter (DAC) is: 1. 63% 2. 15.6% 3. 1.56% 4. 64% Which is not an analog-to-digital (ADC) conversion error? 1. Offset 2. Incorrect code 3. Missing code 4. Differential nonlinearity The difference between analog voltage represented by two adjacent digital codes, or the analog step size, is the: 1. Quantization 2. Accuracy 3. Monotonicity 4. resolution ………………………………. circuits are commonly used in such sensor circuits for generating stimulus signals, due to advantages of accurate frequency control, drift-free performance, etc. 1. Direct digital synthesis (DDS) 2. PLL 3. Hybrid DDS PLL 4. None of the above The output frequency related to the sampling interval of a frequency counter as 1. Directly with the sampling interval 2. Inversely with the sampling interval 3. More precision with longer sampling interval 4. Less precision with longer sampling interval VHSIC stands for 1. Very High Speed Integrated Circuits 2. Very Higher Speed Integration Circuits 3. Variable High Speed Integrated Circuits 4. None of the Mentioned Which of the following frequencies cannot be an intermediate frequency (IF)? 1. 20 MHz 2. 10 MHz 3. 30 MHz 4. 200 MHz (2 x 10)
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h) i) j) Q2. In which kind of waveform is the phase velocity defined? 1. Sinusoidal 2. Rectangular 3. Square 4. Triangular Roll-off factor is 1. The bandwidth occupied beyond the Nyquist Bandwidth of the filter 2. The performance of the filter or device 3. Aliasing effect 4. None of the above Real time systems are embedded in sensors and ________. 1. actuators 2. frames 3. major cycles 4. none e) f) g) h) i) j) Answer the following questions: Short answer type : A local frequency is higher than the received desired signal frequency. True or False. Justify your answer. Differentiate Duplexer and Diplexer. Discuss the tern Interoperability in SDR waveform probability. What are the benefits of multistage rather than single stage structures of a decimator? What do you mean by periodic Jitter? What do you mean by DDS-PLL system? Name the four common ADC and DAC architecture. Describe array calibration. Why FPGA is needed to design DSP processors? Explain the trade-off in using DSP. Q3. a) b) Part – B (Answer any four questions) Explain the design principle of Software Radio. Describe the characteristics and benefits of Software Radio. (10) (5) Q4. a) b) Describe RF Front-End topologies. Describe ADC and DAC distortion. (10) (5) Q5. a) (10) b) Explain the Timing recovery in digital receivers using multirate digital filters. With neat diagram. Explain briefly about sample rate conversion principle. Q6. a) b) Explain the ROM compression techniques. Performance of direct digital synthesis system. (10) (5) Q7. a) Describe the fully adaptive array approach for beam forming system with neat diagram. Describe the overload distortion in ADC. (10) Describe the algorithms for Receiver Space time adaptive signal processing (STAP). Describe the multi processing using real time operating system (RTOS). (10) Explain the design of digital beam forming of Transmitter and Receiver implementation with neat diagram. Describe the benefits of smart antenna. (10) a) b) c) d) b) Q8. a) b) Q9. a) b) (2 x 10) (5) (5) (5) (5)
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