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Previous Year Exam Questions for Digital System Design - DSD of 2018 - BPUT by Bput Toppers

  • Digital System Design - DSD
  • 2018
  • PYQ
  • Biju Patnaik University of Technology Rourkela Odisha - BPUT
  • Electronics and Communication Engineering
  • B.Tech
  • 3 Offline Downloads
  • Uploaded 9 months ago
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Registration No : Total Number of Pages : 03 B.Tech PET5H003 5th Semester Regular / Back Examination 2018-19 DIGITAL SYSTEM DESIGN BRANCH : ECE, ETC Time : 3 Hours Max Marks : 100 Q.CODE : E227 Answer Question No.1 (Part-1) which is compulsory, any EIGHT from Part-II and any TWO from Part-III. The figures in the right hand margin indicate marks. Part- I Short Answer Type Questions (Answer All-10) Q1 a) b) c) Differentiate between combinational and sequential circuits. What is the difference between a latch and a flip flop? Write down the difference between synchronous andasynchronous sequential circuits. d) e) A simple counter is what type of state machine? Justify your answer. Draw a block diagram for a memory unit. f) g) What is the function of a datapath block in a digital system? When does the latches are generated within circuit by the tool during synthesis while designing with HDL. What is the maximum positive and negative number that can be represented by a 5-bit binary number? State Moore’s law. What do understand by a Look up Table(LUT)? h) i) j) (2 x 10) Part- II Q2 Focused-Short Answer Type Questions- (Answer Any EIGHT out of TWELVE) a) Explain about the working of a 4-bit array multiplier. b) c) Write a VHDL code for a full adder in structural modeling style. Obtain the simplified Boolean expression for the outputs F and G in terms of the input variables for the given circuit. (6 x 8)

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d) e) f) g) Explain the difference among a truth table, a state table, a characteristic table, and an excitation table. Explain the difference between a Moore and a Mealy state machine. Write a VHDL code for a negative edge triggered D-type flip-flop with an asynchronous active low reset, a synchronous active-high set, and an active-high clock enable input. Implement the following Boolean functions with a PLA, F1(A, B, C) = ∑ 0, 1, 2, 4 F2(A, B, C) = ∑ 0, 5, 6, 7 h) i) j) k) l) Draw the basic Xilinx architecture for spartan series of FPGAs. Explain each of the block used in the architecture. Write a note on Programmable Array Logic(PAL). Write a VHDL code for detecting a sequence “110” using Moore’s FSM style of modeling. What do you understand by a testbench file. Describe how does the communication takes place between a testbench block and the DUT(Design Under Test). Write a detailed note on Read Only Memory(ROM). Part-III Long Answer Type Questions (Answer Any TWO out of FOUR) Q3 For the given table, a) Draw the corresponding state diagram. b) Tabulate the reduced state table. c) Draw the state diagram for the reduced state table. (16) Q4 Draw the ASMD charts for the following state transitions: a) If x = 1, control goes from state S1 to state S2 ; if x = 0, generate a conditional operation R <= R + 2 and go from S1 to S2 . b) If x = 1, control goes from S1 to S2 and then to S3 ; if x = 0, control goes from S1 to S3. c) Start from state S1; then if xy= 11, go to S2; if xy= 01 go to S3; and if xy= 10, go to S1 ; otherwise, go to S3. (16)

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Q5 The D latch can be constructed with four NAND gates and an inverter as shown below. Consider the following three other ways for obtaining a D latch. In each case, draw the logic diagramand verify the circuit operation. (16) a) Use NOR gates for the SR latch part and AND gates for the other two. An invertermay be needed. b) Use NOR gates for all four gates. Inverters may be needed. c) Use four NAND gates only (without an inverter). This can be done by connecting the output of the upper gate in below figure(the gate that goes to the SR latch) to the inputof the lower gate (instead of the inverter output). Q6 Describe in detail about finite state machines. What are the limitations of designing with fsm. Draw the state diagram for a sequence detector that will detect 101. (16)

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