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# Previous Year Exam Questions for Digital System Design - DSD of 2014 - HITECH by Narayan Sethy

• Digital System Design - DSD
• 2014
• PYQ
• ANNA UNIVERISTY - HITECH
• Electrical and Electronics Engineering
• B.Tech
• 1 Views
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#### Previous Year Exam Questions for Digital System Design - DSD of 2014 - HITECH by Narayan Sethy / 3

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End Semester Examinations - April/May 2014 (R 2008) BE(Full Time) - I I I Semester- Electrical and Electronics Engineering College of Engineering, Anna University Chennai-600 025 Time : 3 Hours E E 9204 - Digital System Design Max Marks :100 Answer A L L Questions Part-A 10 x 2 = 20 1. 2. 3. 4. 5. 6. Realise an XOR gate using NOR gates. Draw the internal structure of an 8 X 1 multiplexer. What is a half adder? What is a PLD ? Find the difference using 15's and 16's complement arithmetic (069)i - (023)i Implement the following function using only one 4:1 mux and minimum number of gates. F(A ,B,C,D) = £ m ( , 3, 4, 5, 9, 11) + £ d( 0, 1) 7. Explain the essential features of VHDL . 8. Draw the logic diagram of the D FF and write the Characteristic equation and Next state table. 9. Construct a divide by 8 ripple counter. 10. What is fundamental mode operation in Asynchronous circuits? 6 6 2 Part-B 5 x 16 =80 11 .(i) Construct Hamming code for the four bit data (1110). Use odd parity. (ii) Construct a full adder . (iii) Explain with example alphanumeric codes. 12 (a) (i) Given the Boolean function Y(A,B,C,D) =A + ABD' + ABCD (;') Convert to standard SOP (ii) Reduce using K-map (4) (8) (4) (4) (4) (iii) Construct circuit using NAND gates only. (ii) Find the reduced POS form using K-map F(A,B,C,D) = TCM(0,6,7,8,12,13,14,15). Implement using NAND gates . (2) (6) (OR) 12(b) (i) Convert to SOP and POS forms (i) Fi(X,Y,Z)=XY + XZ ; (ii) F (X,Y Z) = (X + Y ' ) ( X'+Z) ; 2 (ii) Using K map, simplify the following expressions and implement (4+4)

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them using NAND gates F,(A, B, C, D) = £ m (1, 5, 6, 7,11,12,13) + Id (10,15) F (A, B, C, D) = £ m (0, 2, 5, 7, 8, 10, 13, 15) (4+4) 2 13(a) (i) Implement the function using only one 8x1 multiplexer where the binary inputs A,B,C are connected to the selection lines S ,Si and S respectively. 0 F(A, B, C, D) = 2 2> (0, 2, 3, 6, 8, 9, 11. 13). (4). (ii) Implement the following functions using decoder and gates F,(A, B) = Em (0, 1,3), F ( A , B ) = 7tM(0,2.3) (4) 2 (iii) Draw a ROM to implement the Boolean functions Fj= ABCD+AB'CD'+ A ' B C ' D + A B C ' D ' F =AB'+A'B (8) 2 (OR) 13(b) (i) Implement the following functions using PLA having 3 i/ps , 4 product terms and 3 outputs. Im (3, 5, 6, 7) ; F (A, B, C) = Im (0, 2, 4, 7); F,(A, B, C) = 2 F (A,B,C) = Zm(l,2,4,7). (8) 3 (ii) Implement the functions given in 13(b)(i) using ROM. (8) 14(a) A sequential circuit has three T flip flops A,B,C and one input x . It is described by the following flip flop input functions T = A x ' ; T = A x ; T = B. The output A B c y =A'+x. Derive the state table. Draw the Mealy state diagram. (OR) 14(b)(i) Design a synchronous counter that has the counting sequence 0,3,5,6,7,2,0 . Use T flip flops for realization. (8) (ii) Derive the characteristic equation and excitation equation of J-K Flip flop. (8) 15(a) Design an asynchronous sequential circuit with two inputs x l and x2 and one output z. Initially both inputs and output are equal to zero. When x l or x2 becomes '1 ' z becomes 1. When the second input also becomes 1 the output changes to zero. The output stays at zero until the circuit goes back to initial state. Obtain the primitive flow table and design the circuit using gates. (OR) (16)

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©(b) (i) Explain the difference between asynchronous and synchronous sequential Circuits. (3) (ii) What are the applications of Grey codes ? (3) (iii) Explain the difference between stable and unstable states (iv) Convert the flow table shown in Figure-2 into a transition table 'by assigning the following binary values to the states : a = 00, b = 11 , c = 01. Assign outputs to the don't care states to avoid momentary false outputs. Derive the logic diagram of the circuit. X l X 2 a 00 a,0 01 b, - 11 c 10 a,l b a,- b, b, c,l c a,- b, - c,l c,l Figure-2 (3) (7)