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# Previous Year Exam Questions for Digital System Design - DSD of 2014 - HITECH by Narayan Sethy

• Digital System Design - DSD
• 2014
• PYQ
• ANNA UNIVERISTY - HITECH
• Electrical and Electronics Engineering
• B.Tech
• 27 Views
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#### Previous Year Exam Questions for Digital System Design - DSD of 2014 - HITECH by Narayan Sethy / 3

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End Semester Examinations - April/May 2014 (R 2012) BE(Full Time) - I I I Semester- Electrical and Electronics Engineering College o f Engineering, Anna University Chennai-600 025 Time : 3 Hours EE 8301 - Digital Systems Max Marks :100 Answer A L L Questions Part - A 10 X 2 = 20 1. Realise an X O R gate using N A N D gates. 2. Find the complement and dual o f the Boolean function F(A,B,C) = A B + BC 3. Draw the structure o f an 8 X 4 R O M 4. What is a P L D ? 5. Find the difference using 15's and 16's complement arithmetic (069) (023) 6. Implement the following function using only one 4:1 mux and minimum number o f gates. F(A ,B,C,D) = £ m (2, 3, 4, 5, 9, 11) d( 0, 1) 7. Explain the essential features o f V H D L . 8. Draw the logic diagram o f the T FF and write the Characteristic equation and Next state table. 9. Construct a decade asynchronous UP counter. 10. What is fundamental mode operation in Asynchronous circuits? ]6 16 Part-B 5 x 16 =80 11. (i) Construct Hamming code for B C D 0110. Use even parity. (4) (ii) For the logic circuit shown in Fig-1, find out the logic function performed using Boolean theorems. (iii) Explain w i t h example self-complementing codes. (8) (4)

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12 (a) (i) Given the Boolean function Y ( A , B , C , D ) = A + B C + A B D ' + A B C D (0 Convert to standard SOP (4) (ii) Reduce using K-map (4) (Hi) Construct circuit using N A N D gates only. (2) (ii) Find the reduced POS f o r m using K-map F(A,B,C,D) = TIM(0,6,7,8,12,13,14,15). Implement using N O R gates . (6) (OR) 12(b) (i) Convert to Canonical forms (i) F , ( X , Y , Z ) = X Y + Z ; (ii) F ( X , Y Z ) = ( X + Y ' ) ( X ' + Z ) ; (4+4) 2 (ii) Using K map, simplify the following expressions and implement them using N A N D gates F,(A, B , C, D ) = Zm ( 1 , 5, 6, 7,11,12,13) + £ d (10,15) F ( A , B , C, D ) = 2 Im (0, 2, 5, 7, 8, 10, 13, 15) (4+4) 13(a) (i) Implement the function using only one 4 : 1 mux and gates. F(A, B , C, D ) = Im (0, 2, 3, 6, 8, 9, 11. 13). (4). (ii) Implement the following functions using active low decoder Fi(A,B) = Em(0,l,3), F ( A , B ) = 7tM (0, 2. 3) 2 (Do not convert to SOP) (4) (iii) Draw a R O M to implement the Boolean functions Fi= ABCD+AB'CD'+ A ' B C ' D + A B C ' D ' F =AB'+A'B (8) 2 (OR) 13(b) (i) Implement the following functions using P L A having 3 i/ps , 4 product terms and 2 outputs. F1(A, B , C) = 14(a) Im (3, 5, 6, 7) ; F2(A, B , C) = Im (0, 2, 4, 7). (8) (ii) Implement the functions given i n 13(b)(i) using R O M . (8) A sequential circuit has three T flip flops A , B , C and one input x . It is described by the following f l i p flop input functions T = A x ' ; A

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T = A x ; T = B . The output B c y = A ' + x . Derive the state table. Draw the Mealy state diagram. (OR) 14(b)(i) Design a synchronous counter that has the counting sequence 0,3,5,6,7,2,0 . Use D f l i p flops for realization. (8) (ii) Derive the characteristic equation and excitation equation o f J-K Flip flop. (8) 15(a) Design an asynchronous sequential circuit w i t h two inputs x l and x2 and one output z. Initially both inputs and output are equal to zero. When x l or x2 becomes ' 1 ' z becomes 1. When the second input also becomes 1 the output changes to zero. The output stays at zero until the circuit goes back to initial state. Obtain the primitive f l o w table and design the circuit using gates. (16) (OR) 15(b) (i) Explain the difference between asynchronous and synchronous sequential Circuits. (3) (ii) What are the applications o f Grey codes ? (iii) Explain the difference between stable and unstable states (3) (3) (iv) Convert the f l o w table shown in Figure-2 into a transition table by assigning the following binary values to the states : a = 00, b = 11 , c = 01. Assign outputs to the don't care states to avoid momentary false outputs. Derive the logic diagram o f the circuit. X1x 2 a 00 a,0 01 b, - 11 Jc 10 a,l b a,- b, |b, c,l c a,- b, - c ,1 c,l Figure-2 (7)