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Previous Year Exam Questions for Satellite Communication System - SCS of 2012 - HITECH by Narayan Sethy

  • Satellite Communication System - SCS
  • 2012
  • PYQ
  • Electronics and Communication Engineering
  • B.Tech
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Registration Number END SEMESTER ARREAR EXAMINATION - NOVEMBER 2012 DEGREE BRANCH SEMESTER CODE NO./ SUBJECT B.E.(Full Time) - Regulation 2008 Electronics and Communication Engineering Eight EC 9031 - Satellite Communication Duration : 3 Hours Max. Marks = 100 Answer ALL the questions. PART A (10x2 = 20 marks) 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. List out the fundamental Newtonian equations that are used to derive the motion of a satellite in its orbit. Given that the earth rotates once per sidereal day of 23 h 56 min 4.09 s, show that the radius of the GEO is 42,164.17 km. What do you understand by Sun transit outage. Draw the block diagram of a simplified double conversion transponder for operation at 14/11 GHz band. Highlight the difference between QPSK and QAM modulation schemes. What is the advantage of interleaving the data bits at the transmitter and de-interleaving them at the receiver end. What is the necessity for unique word detection in TDMA based satellite systems. Illustrate your understanding about spreading of a signal. What do understand by Differential GPS. Where does VSAT systems find their widest applications. PART B ( 5 x 16 = 80 marks ) 11. What is meant by DBS service and how does this differ from home reception of satellite TV signals in the C-band ? With the aid of a block schematic describe the functioning of the indoor receiving unit of a satellite TV / FM receiving system intended for home reception. 12a. What are Kepler's three laws of planetary motion. Give the mathematical formulation of Kepler's third law of planetary motion. What do the terms apogee and perigee mean when used to describe the satellite orbit. A satellite in an elliptical orbit around the earth has an apogee of 39,152 km and a perigee of 500 km. What is the orbital period of this P.T.O | i

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13 a) Draw with neat circuit diagram and timing diagram of BCD ripple counter and explain its operation (or) Reduce the number of states in the following state table and tabulate the reduced state table b) Present state Next state x=0 f b d c f e a a G d c f b h g a g a b c d e f g h 14 Output Z x = 0 x=l 0 0 0 0 0 •o 0 1 0 0 1 1 1 0 1 0 Implement the following functions using PLA a) f,(A,B,C) = £(1,3,4,6,7) b) f (A,B,C) = 1(2,4,6,7) c) f (A,B,C) = £(0,1,2,4,6,7) (or) Explain with neat diagram the various modules present in FPGA XL4000 and its functions a) 2 3 b) 15 a)i) ii) Draw the circuit diagram and explain the operation of three input NAND gate using CMOS .gate (10 marks) Draw the circuit diagram of CMOS inverter and explain its operation (6 marks) (or) b) i) ii) Explain with neat diagram and working of two input NOR gate using RTL (6 marks) Explain with neat circuit diagram the operation of three state TTL gate (10 marks)

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