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Previous Year Exam Questions for CAD For VLSI - CAD of 2012 - HITECH by Narayan Sethy

  • CAD For VLSI - CAD
  • 2012
  • PYQ
  • ANNA UNIVERISTY - HITECH
  • Electronics and Communication Engineering
  • B.Tech
  • 6 Views
  • Uploaded 2 months ago
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Roll No. B.E. / B.Tech (Full Time) D E G R E E END S E M E S T E R EXAMINATIONS, NOV. / D E C . 2012 ELECTRONICS AND COMMUNICATION ENGINEERING BRANCH EIGHT SEMESTER E C 9045 - CAD for VLSI (REGULATIONS 2008) Max. Marks: 100 Time: 3 Hours Answer All Questions Part-A 1) (10 x 2 = 20 Marks) Define "data structure" and "algorithm". 2) What are the different complexity classes of algorithm?.Arrange them in the increasing order of time complexities. 3) How is the placement algorithms grouped? 4) Write short notes on problem formulation. 5) Give the major objectives of floorplanning process. 6) Write a short on shape function in the floorplanning process. 7) List the Various Kinds of simulation process. 8) Prepare the comparison table between gate-level modeling and switch-level modeling. 9) What is meant by scheduling? 10) Why the high level synthesis model is necessary for hardware implementation process? Part-B ( 5 x 1 6 = 80 Marks) 11) (a) Describe in detail about the various VLSI design automation tools in the physical design cycle. (16) 12) (a) Write and explain the pseudo code describe of Prim's minimum spanning tree algorithm. (16) (or) (b) Describe in detail about the Bellman-Ford algorithm. Page 1 of 2 (16)

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13) (a) Describe in detail about the various channel routing models (16) (or) (b) Explain in detail about the Rectilinear Steiner-tree construction in global routing technique. (16) 14) <a) Explain the basic version of Lee's algorithm for area routing. (16) <or) (b) Compute the positive co-factor of an ROBOD. List out the various factors. (16) 15. (a) Mention the various hardware components that can be used by a system for the processing of high level synthesis. (16) (or) (b) Describe the Force directed scheduling algorithm. Page 2 of 2 {16)

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