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Computer-Aided Design for VLSI Kartik Mohanram Dept. of Electrical and Computer Engineering Rice University Today „ VLSI design flow „ „ EDA Tools „ „ System drivers [ITRS roadmap] Synopsys, Cadence, Mentor Conferences „ DAC, ICCAD, DATE, ITC, VTS, ISPD, ISLPED, … ELEC & COMP 523 Computer-Aided Design for VLSI 2 1

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System Drivers „ „ „ „ Future semiconductor manufacturing and design technology capability is developed in response to economic drivers within the worldwide semiconductor industry. 3 Product classes previously „ Microprocessor (MPU) „ Dynamic random-access memory (DRAM) „ Application-specific integrated circuit (ASIC) Some mention of system-on-chip (SoC) and analog/mixedsignal (AMS) circuits Assumption – technological advances need only be straight ahead and linear „ Deployed in all semiconductor products „ Specifics of product classes not required ELEC & COMP 523 Computer-Aided Design for VLSI 3 System Drivers „ Today, introduction of new technology solutions is increasingly application-driven, with products for different markets using different combinations of technologies at different times „ „ „ General-purpose digital microprocessors for personal computers are being joined as drivers by mixed-signal systems for wireless communication and embedded applications Low-power battery-powered mobile devices In-house, single-source chip designs are being supplanted by SoC designs that incorporate building blocks from multiple sources ELEC & COMP 523 Computer-Aided Design for VLSI 4 2

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System Drivers [ITRS 2001] „ 3 system drivers „ „ „ „ High-volume custom microprocessor (MPU) Analog/mixed-signal (AMS) System-on-chip (SoC) What about „ „ Application-specific integrated circuits (ASICs)? High-volume custom memory (DRAM)? „ Commodity nature ELEC & COMP 523 Computer-Aided Design for VLSI 5 Driver Classes „ Driver classes distinguished according to „ „ „ „ „ Cost = manufacturing cost + design cost Manufacturing cost „ Non-recurring engineering (NRE) cost (masks, tools, etc.) + „ Silicon cost (raw wafers + processing + test) System cost = F(functionality, No. I/Os, packaging cost, power, speed, etc.) Time-to-market Production volume ELEC & COMP 523 Computer-Aided Design for VLSI 6 3

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MPUs „ Performance and manufacturing cost issues outweigh design or other NRE cost issues „ „ „ Primarily because these chips can potentially produce large profits „ From very large sales volumes Large volumes alone neither necessary nor sufficient to warrant custom design, special process engineering and equipment, etc. „ Key – expected return on combined NRE and manufacturing investment must be positive 3 dominant sub-classes „ MPUs, memory, and re-programmable devices (e.g., field-programmable gate arrays (FPGA)) ELEC & COMP 523 Computer-Aided Design for VLSI 7 MPUs „ Use THE most aggressive design styles and manufacturing technologies „ „ It is for these high-volume parts that „ Changes to the manufacturing flow are made „ New design styles and supporting tools are created (the large revenue streams can pay for new tool creation) „ Subtle circuits’ issues are uncovered (not all risks taken by designers work out). Thus, while MPUs (and high-volume custom designs in general) are extremely labor-intensive, they create new technology and automation methods (in both design and fabrication) that are leveraged by the entire industry. ELEC & COMP 523 Computer-Aided Design for VLSI 8 4