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Note for Digital System Design - DSD By kotireddy praveen kumar reddy

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R.Ravindraiah Lecture Notes Digital System Design JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR B. Tech III-ISem. (ECE) LTPC 3 103 15A04504 DIGITAL SYSTEM DESIGN Course Objectives:  To be able to use computer-aided design tools for development of complex digital logic circuits  To be able to model, simulate, verify, analyze, and synthesize with hardware description languages  To be able to design and prototype with standard cell technology and programmable logic  To be able to design tests for digital logic circuits, and design for testability Course Outcomes:  Capable of using Computer-aided design tools to model, simulate, verify, analyze, and synthesize complex digital logic circuits.  Efficient designing of any Digital System using basic structure ICs .  Able to design and prototype with standard cell technology and programmable logic.  Apply design test for digital logic circuits, and design for testability. UNIT-I CMOS LOGIC: Introduction to logic families, CMOS logic, CMOS logic families; BIPOLAR LOGIC AND INTERFACING: Bipolar logic, Transistor logic, TTL families, CMOS/TTL interfacing, low voltage CMOS logic and interfacing, Emitter coupled logic, Comparison of logic families, Familiarity with standard 74-series and CMOS 40- series-ICs – Specifications. UNIT-II HARDWARE DESCRIPTION LANGUAGES: HDL Based Digital Design, The VHDL Hardware Description Language–Program Structure, Types, Constants and Arrays, Functions and procedures, Libraries and Packages, Structural design elements, Dataflow design elements, Behavioral design elements, The Time Dimension, Simulation, Test Benches, VHDL Features for Sequential Logic Design, Synthesis UNIT-III COMBINATIONAL LOGIC DESIGN PRACTICES: Description of basic structures like Decoders, Encoders, Comparators, Multiplexers ( 74 –series MSI); Design of complex Combinational circuits using the basic structures; Designing Using combinational PLDs like PLAs, PALs ,PROMs CMOS PLDs; Adders & sub tractors, ALUs, Combinational multipliers; VHDL models for the above standard building block ICs. UNIT-IV SEQUENTIAL MACHINE DESIGN PRACTICES: Review of design of State machines; Standard building block ICs for Shift registers, parallel / serial conversion, shift register counters, Ring counters; Johnson counters, LFSR counter; VHDL models for the above standard building block ICs.Synchronous Design example using standard ICs UNIT –V Design Examples (using VHDL): Barrel shifter, comparators, floating-point encoder, and dual parity encoder. Sequential logic Design: Latches & flip flops, PLDs, counters, shift register and their VHDL models. Text Books: 1. John F.Wakerly ,“Digital Design Principles and Practices” 4th edition, Pearson Education., 2009 2. Charles H.Roth,Jr., “Fundamentals of Logic Design” 5th edition , CENGAGE Learning 2012. References: 1. M.Morris Mano and Michael D. Cilleti., “Digital Logic Design” 4th edition Pearson Education., 2013 2. Stephen Brown and ZvonkoVranesic, “Fundamentals of digital logic with VHDL design” 2nd edition McGraw Hill Higher Education. 3. J. Bhasker, “A VHDL PRIMER” 3rd edition Eastern Economy Edition, PHI Learning,2010. CREC Dept. of ECE Page|2

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R.Ravindraiah Lecture Notes Digital System Design UNIT - I CMOS LOGIC CREC Dept. of ECE Page|3

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R.Ravindraiah Lecture Notes Digital System Design UNIT 1(CMOS LOGIC) Logic Signals and Gates Digital logic hides the pitfalls of the analog world by mapping the infinite set of real values for a physical quantity into two subsets corresponding to just two possible numbers or logic values—0 and 1. As a result, digital logic circuits can be analyzed and designed functionally, using switching algebra, tables, and other abstract means to describe the operation of well-behaved 0s and 1s in a circuit. A logic value, 0 or 1, is often called a binary digit, or bit. If an application requires more than two discrete values, additional bits may be used, with a set of n bits representing 2n different values. With most phenomena, there is an undefined region between the 0 and 1 states (e.g., voltage = 1.8 V, dim light, capacitor slightly charged, etc.). This undefined region is needed so that the 0 and 1 states can be unambiguously defined and reliably detected. Noise can more easily corrupt results if the boundaries separating the 0 and 1 states are too close. When discussing electronic logic circuits such as CMOS and TTL, digital designers often use the words ―LOWǁ and ―HIGHǁ in place of ―0ǁ and ―1ǁ to remind them that they are dealing with real circuits, not abstract quantities: LOW A signal in the range of algebraically lower voltages, which is interpreted as a logic 0. HIGH A signal in the range of algebraically higher voltages, which is interpreted as a logic 1. Note that the assignments of 0 and 1 to LOW and HIGH are somewhat arbitrary. Assigning 0 to LOW and 1 to HIGH seems most natural, and is called positive logic. The opposite assignment, 1 to LOW and 0 to HIGH, is not often used, and is called negative logic. Because a wide range of physical values represent the same binary value, digital logic is highly immune to component and power supply variations and noise. Furthermore, buffer amplifier circuits can be used to regenerate ―weakǁ values into ―strongǁ ones, so that digital signals can be transmitted over arbitrary distances without loss of information. For example, a buffer amplifier for CMOS logic converts any HIGH input voltage into an output very close to 5.0 V, and any LOW input voltage into an output very close to 0.0 V. A logic circuit can be represented with a minimum amount of detail simply as a ―black boxǁ with a certain number of inputs and outputs. For example, Figure shows a logic circuit with three inputs and one output. However, this representation does not describe how the circuit responds to input signals. From the point of view of electronic circuit design, it takes a lot of information to describe the precise electrical behavior of a circuit. However, since the inputs of a digital logic circuit can be viewed as taking on only discrete 0 and 1 values, the circuit’s ―logicalǁ operation can be described with a table that ignores electrical behavior and lists only discrete 0 and 1 values. CREC Dept. of ECE Page|4

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